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data sheet november, 2002 www.latticesemi.com orca ? series 4 fpgas introduction built on the series 4 recon gurable embedded sys- tem-on-a-chip (soc) architecture, lattice introduces its new family of generic field-programmable gate arrays (fpgas). the high-performance and highly v ersatile architecture brings a new dimension to bringing network system designs to market in less time than ever before. this new device family offers many new features and architectural enhancements not available in any earlier fpga generations. bring- ing together highly e xible sram-based programma- b le logic, powerful system features, a rich hierarchy of routing and interconnect resources, and meeting m ultiple interface standards, the series 4 fpga accommodates the most complex and high-perfor- mance intellectual property (ip) network designs. programmable features high-performance platform design: ? 0.16 m 7-level metal technology. ? internal performance of >250 mhz. ? i/o performance of >420 mhz. ? meets multiple i/o interface standards. ? 1.5 v operation (30% less power than 1.8 v operation) translates to greater performance. tr aditional i/o selections: ? lvttl (3.3v) and lvcmos (2.5 v and 1.8 v) i/os. ? per pin-selectable i/o clamping diodes provide 3.3 v pci compliance. ? individually programmable drive capability: 24 ma sink/12 ma source, 12 ma sink/6 ma source, or 6 ma sink/3 ma source. ? two slew rates supported (fast and slew-lim- ited). ? fast-capture input latch and input ip- op (ff)/latch for reduced input setup time and zero hold time. ? fast open-drain drive capability. ? capability to register 3-state enable signal. ? off-chip clock drive capability. ? two-input function generator in output path. new programmable high-speed i/o: ? single-ended: gtl, gtl+, pecl, sstl3/2 (class i and ii), hstl (class i, iii, and iv), zbt, and ddr. ? double-ended: ldvs, bused-lvds, and l vpecl. programmable (on/off) internal parallel termination (100 ? ) also supported for these i/os. tab le 1. orca series 4?available fpga logic * the embedded system bus and mpi are not included in the above gate counts. the system gate ranges are derived from the followi ng: minimum system gates assumes 100% of the pfus are used for logic only (no pfu ram) with 40% ebr usage and 2 plls. maximum system gates assumes 80% of the pfus are for logic, 20% are used for pfu ram, with 80% ebr usage and 6 plls. note: devices are not pinout compatible with orca series 2/3. device rows columns pfus user i/o luts ebr blocks ebr bits (k) usable* gates (k) or4e02 26 24 624 405 4,992 8 74 201?397 or4e04 36 36 1,296 466 10,368 12 111 333?643 or4e06 46 44 2,024 466 16,192 16 148 471?899
ta b le of contents contents page contents page 2 lattice semiconductor data sheet november, 2002 orca series 4 fpgas introduction ................................................................ 1 programmable features ............................................ 1 system features ....................................................... 4 product description ................................................... 5 architecture overview ..........................................5 programmable logic cells ........................................ 6 programmable function unit ...............................7 look-up table operating modes .......................10 supplemental logic and interconnect cell ........20 plc latches/flip-flops ......................................24 embedded block ram (ebr) .................................. 26 ebr features ....................................................26 routing resources .................................................. 31 clock distribution network ...................................... 31 global primary clock nets .................................31 secondary clock and control nets ....................31 secondary edge clock nets and fast edge clock nets ...................................31 cycle stealing ....................................................32 programmable input/output cells (pic) .................. 32 programmable i/o ..............................................32 inputs .................................................................35 outputs ..............................................................36 i/o banks and groups ....................................... 37 special function blocks .......................................... 39 single function blocks .......................................47 microprocessor interface (mpi) ............................... 49 embedded system bus (esb) ...........................49 phase-locked loops (plls) ................................... 53 fpga states of operation ....................................... 56 initialization ........................................................56 power supply sequencing .................................57 configuration ......................................................57 start-up ..............................................................57 reconfiguration ..................................................61 partial reconfiguration .......................................61 other configuration options ..............................61 configuration data format .................................61 using isplever to generate configuration ram data ...............................61 configuration data frame ..................................62 bit stream error checking .................................64 fpga configuration modes ..................................... 64 master parallel mode .........................................65 master serial mode ............................................66 asynchronous peripheral mode .........................67 microprocessor interface mode ..........................68 slave serial mode ..............................................72 slave parallel mode ...........................................72 daisy-chaining ...................................................73 daisy-chaining with boundary-scan ..................74 absolute maximum ratings ..................................... 75 recommended operating conditions ................75 electrical characteristics ......................................... 76 power estimation ..................................................... 77 estimating power dissipation .................................. 77 timing characteristics ............................................. 78 configuration timing ..........................................92 readback timing ............................................ 100 pin information ...................................................... 101 pin descriptions .............................................. 101 package compatibility ..................................... 105 352-pin pbga pinout ...................................... 107 416-pin bgam pinout ..................................... 116 680-pin pbgam pinout ................................... 126 package thermal characteristics summary ......... 142 ja ................................................................. 142 jc ................................................................. 142 jc ................................................................. 143 jb ................................................................. 143 package thermal characteristics .......................... 144 package coplanarity ............................................. 144 heat sink vendors for bga packages .................. 144 package parasitics ................................................ 145 package outline diagrams .................................... 146 terms and definitions ..................................... 146 352-pin pbga ................................................. 147 416-pin pbgam .............................................. 148 680-pin pbgam .............................................. 149 ordering information .............................................. 150
lattice semiconductor 3 data sheet november, 2002 orca series 4 fpgas programmable features (continued) new capability to (de)multiplex i/o signals: ? new double data rate on both input and output at r ates up to 350 mhz (700 mhz effective rate). ? new 2x and 4x downlink and uplink capability per i/o (i.e., 50 mhz internal to 200 mhz i/o). enhanced twin-quad programmable function unit (pfu): ? eight 16-bit look-up tables (luts) per pfu. ? nine user registers per pfu, one following each lut and organized to allow two nibbles to act independently, plus one extra for arithmetic opera- tions. ? new register control in each pfu has two inde- pendent programmable clocks, clock enables, local set/reset, and data selects. ? new lut structure allows e xible combinations of lut4, lut5, new lut6, 4 to 1 mux, new 8 to 1 mux, and ripple mode arithmetic functions in the same pfu. ? 32 x 4 ram per pfu, con gurable as single- or dual-port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the slic decoders as bank drivers. ? soft-wired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu through fast internal routing which reduces routing congestion and improves speed. ? flexible fast access to pfu inputs from routing. ? fast-carry logic and routing to all four adjacent pfus for nibble-, byte-wide, or longer arithmetic functions, with the option to register the pfu carry-out. abundant high-speed buffered and nonbuffered rout- ing resources provide 2x average speed improve- ments over previous architectures. hierarchical routing optimized for both local and glo- bal routing with dedicated routing resources. this results in faster routing times with predictable and ef cient performance. slic provides eight 3-statable buffers, up to 10-bit decoder, and pa l ?-like and-or-invert (aoi) in each programmable logic cell. improved built-in clock management with program- mable phase-locked loops (pplls) provide optimum clock modi cation and conditioning for phase, fre- quency, and duty cycle from 15 mhz up to 420 mhz. multiplication of the input frequency up to 64x, and division of the input frequency down to 1/64x possi- ble. new 200 mhz embedded quad-port ram blocks, two read ports, two write ports, and two sets of byte lane enables. each embedded ram block can be con g- ured as: ? 1-512 x 18 (quad-port, two read/two write) with optional built in arbitration. ? 1-256 x 36 (dual-port, one read/one write). ? 1-1k x 9 (dual-port, one read/one write). ? 2-512 x 9 (dual-port, one read/one write for each). ? 2 rams with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). ? supports joining of ram blocks. ? two 16 x 8-bit content addressable memory (cam) support. ? fifo 512 x 18, 256 x 36, 1k x 9 or dual 512 x 9. ? constant multiply (8 x 16 or 16 x 8). ? dual-variable multiply (8 x 8). embedded 32-bit internal system bus plus 4-bit par- ity interconnects fpga logic, microprocessor inter- f ace (mpi), embedded ram blocks, and embedded standard cell blocks with 100 mhz bus performance. included are built-in system registers that act as the control and status center for the device. built-in testability: ? full boundary scan ( ieee ? ? 1149.1 and draft 1149.2 joint test access group (jtag)). ? programming and readback through boundary scan port compliant to ieee draft 1532:d1.7. ? ts_all testability function to 3-state all i/o pins. ? new temperature sensing diode. new cycle stealing capability allows a typical 15% to 40% internal speed improvement after nal place and route. this feature also enables compliance with many setup/hold and clock-to-out i/o speci cations and may provide reduced ground bounce for output b uses by allowing e xible delays of switching output b uffers.
4 4 lattice semiconductor data sheet november, 2002 orca series 4 fpgas system features pci local bus compliant. improved powerpc ? ? ? ? ? /powerquicc ? mpc 860 and po w erpc ii mpc8260 high-speed synchronous microprocessor interface can be used for con gura- tion, readback, device control, and device status, as w ell as for a general-purpose interface to the fpga logic, rams, and embedded standard cell blocks. glueless interface to synchronous po w erpc proces- sors with user-con gurable address space provided. new embedded amba ? ? speci cation 2.0 ahb sys- tem bus ( arm ? ? ? ? processor) facilitates communica- tion among the microprocessor interface, con guration logic, embedded block ram, fpga logic, and embedded standard cell blocks. new network plls meet itu-t g.811 speci cations and provide clock conditioning for ds-1/e-1 and sts-3/stm-1 applications. va r iable size bused readback of con guration data capability with the built-in microprocessor interface and system bus. internal, 3-state, bidirectional buses with simple con- trol provided by the slic. new clock routing structures for global and local clocking signi cantly increases speed and reduces skew (<200 ps for or4e04). new local clock routing structures allow creation of localized clock trees. tw o new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved setup/hold and clock to out performance. new double-data rate (ddr) and zero-bus turn- around (zbt) memory interfaces support the latest high-speed memory interfaces. new 2x/4x uplink and downlink i/o capabilities inter- f ace high-speed external i/os to reduced speed internal logic. meets universal test and operations phy interface f or atm (utopia) levels 1, 2, and 3. also meets proposed speci cations for utopia level 4, pos- phy level 3 (2.5 gbits/s), and pos-phy 4 (10 gbits/s) interface standards for packet-over-sonet as de ned by the saturn group. isplever development system software. supported by industry-standard cae tools for design entry, syn- thesis, simulation, and timing analysis.
lattice semiconductor 5 data sheet november, 2002 orca series 4 fpgas product description architecture overview the orca series 4 architecture is a new generation of sram-based programmable devices from lattice. it includes enhancements and innovations geared toward today?s high-speed systems on a single chip. designed with networking applications in mind, the series 4 fam- ily incorporates system-level features that can further reduce logic requirements and increase system speed. orca series 4 devices contain many new patented enhancements and are offered in a variety of pack- ages, and speed grades. the hierarchical architecture of the logic, clocks, rout- ing, ram and system level blocks create a seamless merge of fpga and asic designs. modular hardware and software technologies enable system-on-chip inte- gr ation with true plug and play design implementation. the architecture consists of four basic elements: pro- gr ammable logic cells (plcs), programmable input/out- put cells (pios), embedded block rams (ebrs), and system-level features. a high-level block diagram is shown in figure 1. these elements are interconnected with a rich routing fabric of both global and local wires. an array of plcs and its associated resources are sur- rounded by common interface blocks (cibs) which pro- vide an abundant interface to the adjacent pios or system blocks. routing congestion around these criti- cal blocks is eliminated by the use of the same routing f abric implemented within the programmable logic core. pics provide the logical interface to the pios which provide the boundary interface off and onto the device. also the interquad routing blocks (hiq, viq) separate the quadrants of the plc array and provide the global routing and clocking elements. each plc contains a pfu, slic, local routing resources, and con guration ram. most of the fpga logic is per- fo r med in the pfu, but decoders, pa l -like functions, and 3-state buffering can be performed in the slic. the pios provide device inputs and outputs and can be used to register signals and to perform input demul- tiplexing, output multiplexing, uplink and downlink func- tions, and other functions on two output signals. the series 4 architecture integrates macrocell blocks of memory known as ebr. the blocks run horizontally across the plc array and provide e xible memory functionality. large blocks of 512x18 quad-port ram compliment the existing distributed pfu memory. the ram blocks can be used to implement ram, rom, fifo, multiplier, and cam, typically without the use of pfus for implementation. system-level functions such as a microprocessor inter- f ace, plls, embedded system bus elements (located in the corners of the array), the routing resources, and con guration ram are also integrated elements of the architecture. f or series 4 fpscs, all pio buffers and logic are replaced by the embedded logic core on the side of the device. the four plls on the right side of the device (two in the upper right corner and two in the lower right corner) are removed and the embedded system bus e xtends into the fpsc section.
6 lattice semiconductor data sheet november, 2002 orca series 4 fpgas product description (continued) note: for fpscs, all i/os and the four plls on the right side of the device are replaced with the embedded core. 5-7536(f)a figure 1. series 4 top level diagram programmable logic cells the plcs are arranged in an array of rows and columns. the location of a plc is indicated by its row and column so that a plc in the second row and the third column is r2c3. the array of actual plcs for every device begins with r3c2 in all series 4 generic fpgas. pios are located on all four sides of the fpga. every group of four pios on the device edge have an associated pic. the plc consists of a pfu, slic, and routing resources. each pfu within a plc contains eight 4-input (16-bit) luts, eight latches/ffs, and one additional ff that may be used independently or with arithmetic functions. the pfu is the main logic element of the plc, containing elements for both combinatorial and sequential logic. combinatorial logic is done in luts located in the pfu. the pfu can be used in different modes to meet dif- f erent logic requirements. the luts twin-quad architecture provides a con gurable medium-/large-grain architec- ture that can be used to implement from one to eight independent combinatorial logic functions or a large number of complex logic functions using multiple luts. the e xibility of the lut to handle wide input functions, as well as m ultiple smaller input functions, maximizes the gate count per pfu while increasing system speed. the pfu is organized in a twin-quad fashion: two sets of four luts and ffs that can be controlled independently. each pfu has two independent programmable clocks, clock enables, local set/reset, and data selects. luts may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be con- gured as a synchronous 32x4 single- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset. embedded system bus pic plc microprocessor interface (mpi) pfu slic fpga/system bus interface plls embedded block ram high-speed i/os clock pins pio replaced by embedded ip core for fpscs (all 4 sides) (all 4 corners)
lattice semiconductor 7 data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) the luts can be programmed to operate in one of three modes: combinatorial, ripple, or memory. in com- binatorial mode, the luts can realize any 4-, 5-, or 6-input logic function and many multilevel logic func- tions using orca ?s swl connections. in ripple mode, the high-speed carry logic is used for arithmetic func- tions, comparator functions, or enhanced data path functions. in memory mode, the luts can be used as a 32x4 synchronous read/write or rom, in either single- or dual-port mode. the slic is connected from plc routing resources and from the outputs of the pfu. it contains eight 3-state, bidirectional buffers and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert to perform pa l -like functions. the 3-state drivers in the slic and their direct connections from the pfu outputs make fast, true 3-state buses possible within the fpga. programmable function unit the pfus are used for logic. each pfu has 53 exter- nal inputs and 20 outputs and can operate in several modes. the functionality of the inputs and outputs depends on the operating mode. the pfu uses 36 data input lines for the luts, eight data input lines for the latches/ffs, eight control inputs (clk[1:0], ce[1:0], lsr[1:0], sel[1:0]), and a carry input (cin) for fast arithmetic functions and general- purpose data input for the ninth ff. there are eight combinatorial data outputs (one from each lut), eight latched/registered outputs (one from each latch/ff), a carry-out (cout), and a registered carry-out (reg- cout) that comes from the ninth ff. the carry-out sig- nals are used principally for fast arithmetic functions. there are also two dedicated f6 mode outputs which are for the 6-input lut function and 8 to 1 mux. figure 2 and figure 3 show high-level and detailed views of the ports in the pfu, respectively. the eight sets of lut inputs are labeled as k0 through k7 with each of the four inputs to each lut having a suf x of _x, where x is a number from 0 to 3. there are four f5 inputs labeled a through d. these are used for additional lut inputs for 5- and 6-input luts or as a selector for multiplexing two 4-input luts. f our adjacent lut4s can also be multiplexed together with a 4 to 1 mux to create a 6-input lut. the eight direct data inputs to the latches/ffs are labeled as din[7:0]. registered lut outputs are shown as q[7:0], and combinatorial lut outputs are labeled as f[7:0]. the pfu implements combinatorial logic in the luts and sequential logic in the latches/ffs. the luts are static random access memory (sram) and can be used for read/write or rom. each latch/ff can accept data from its associated lut. alternatively, the latches/ffs can accept direct data from din[7:0], eliminating the lut delay if no combina- torial function is needed. additionally, the cin input can be used as a direct data source for the ninth ff. the lut outputs can bypass the latches/ffs, which reduces the delay out of the pfu. it is possible to use the luts and latches/ffs more or less independently, allowing, for instance, a comparator function in the luts simultaneously with a shift register in the ffs.
8 lattice semiconductor data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) 5-5752(f)a figure 2. pfu ports the pfu can be con gured to operate in four modes: logic mode, half-logic mode, ripple mode, and memory (ram/rom) mode. in addition, ripple mode has four submodes and ram mode can be used in either a single- or dual-port memory fashion. these submodes of operation are discussed in the following sections. f5d k7_0 k7_1 k7_2 k7_3 k6_0 k6_1 k6_2 k6_3 k5_0 k5_1 k5_2 k5_3 k4_0 k4_1 k4_2 k4_3 f5c din7 din6 din5 din4 din3 din2 din1 din0 cin f5b k3_0 k3_1 k3_2 k3_3 k2_0 k2_1 k2_2 k2_3 k1_0 k1_1 k1_2 k1_3 k0_0 k0_1 k0_2 k0_3 f5a programmable function unit (pfu) q7 q6 q5 q4 q3 q2 q1 q0 cout regcout f7 f6 f5 f4 f3 f2 f1 f0 sel[0:1] ce[0:1] clk[0:1] lsr[0:1] lut603 lut647
lattice semiconductor 9 data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) 5-9714(f) note: all multiplexers without select inputs are con guration selector multiplexers. figure 3. simpli ed pfu diagram k3_0mux k7_0mux d0 d1 sd sp ck lsr reg7 reset set q7 f7 0 din7 din7mux d0 d1 sd sp ck lsr reg6 reset set q6 f6 0 din6 din6mux d0 d1 sd sp ck lsr reg5 reset set q5 f5 0 din5 din5mux d0 d1 sd sp ck lsr reg4 reset set q4 f4 0 din4 din4mux lut647 0 a b c d a b c d a b c d a b c d fsdmux k7_2mux k6_0mux k6_2mux amux h7h6mux k7 k6 k5 k4 fscmux h5h4mux lut6mux f5d k7_0 k7_1 k7_2 k7_3 k6_0 k6_1 k6_2 k6_3 k5_0 k5_1 k5_2 k5_3 k4_0 k4_1 k4_2 f5c k4_3 d0 d1 sd sp ck lsr reg3 reset set q3 f3 0 din3 din3mux d0 d1 sd sp ck lsr reg2 reset set q2 f2 0 din2 din2mux d0 d1 sd sp ck lsr reg1 reset set q1 f1 0 din1 din1mux d0 d1 sd sp ck lsr reg0 reset set del0 del1 del2 q0 f0 0 din0 din0mux lut603 0 a b c d a b c d a b c d a b c d fsbmux k3_2mux k2_0mux k2_2mux bmux h3h2mux k3 k2 k1 k0 f5amux h1h0mux lut6mux f5b k3_0 k3_1 k3_2 k3_3 k2_0 k2_1 k2_2 k2_3 k1_0 k1_1 k1_2 k1_3 k0_0 k0_1 k0_2 f5a k0_3 0 clk1 clk1mux 0 sel1 sel1mux 1 ce1 ce1mux ce47mux 0 lsr1 lsr1mux lsr47mux 0 cin 1 0 0 clk0 clk0mux 0 sel0 sel0mux 1 ce0 ce0mux cebmux 0 lsr0 lsr0mux ce03mux 1 0 lsrbmux lsr03mux 1 0 d0 sp ck lsr reg8 reset set reccout cout sr1modeattr sr1mode ce1_over_lsr1 lsr1_over_ce1 rsync1 sr0modeattr sr0mode ce0_over_lsr0 lsr0_over_ce0 async0 regmode_top ff latch reg 4 through 7 this is always a flipflop regmode_bot ff latch reg 0 through 3 logic mlogic ripple ram rom enabled disabled gsr pfu modes cinmux 0 0 del3 del0 del1 del2 del3 del0 del1 del2 del3 del0 del1 del2 del3 del0 del1 del2 del3 del0 del1 del2 del3 del0 del1 del2 del3 del0 del1 del2 del3 del0 del1 del2 del3
10 lattice semiconductor data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) look-up table operating modes the operating mode affects the functionality of the pfu input and output ports and internal pfu routing. for exam- ple, in some operating modes, the din[7:0] inputs are direct data inputs to the pfu latches/ffs. in memory mode, the same din[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into lut memory. ta b le 2 lists the basic operating modes of the lut. figure 4?figure 7 show block diagrams of the lut operating modes. the accompanying descriptions demonstrate each mode?s use for generating logic. ta b le 2. look-up table operating modes pfu control inputs each pfu has eight routable control inputs and an active-low, asynchronous global set/reset (gsrn) signal that affects all latches and ffs in the device. the eight control inputs are clk[1:0], lsr[1:0], ce[1:0], and sel[1:0], and their functionality for each logic mode of the pfu is shown in table 3. the clock signal to the pfu is clk, ce stands for clock enable, which is its primary function. lsr is the local set/reset signal that can be con gured as synchronous or asynchronous. the selection of set or reset is made for each latch/ff and is not a function of the signal itself. sel is used to dynamically select between direct pfu input and lut output data as the input to the latches/ffs. all of the control signals can be disabled and/or inverted via the con guration logic. a disabled clock enable indicates that the clock is always enabled. a disabled lsr indicates that the latch/ff never sets/resets (except from gsrn). a disabled sel input indicates that din[7:0] pfu inputs are routed to the latches/ffs. ta b le 3. control input functionality mode function logic 4-, 5-, and 6-input luts; softwired luts; latches/ffs with direct input or lut input; cin as direct input to ninth ff or as pass through to cout. half logic/ half ripple upper four luts and latches/ffs in logic mode; lower four luts and latches/ffs in ripple mode; cin and ninth ff for logic or ripple functions. ripple all luts combined to perform ripple-through data functions. eight lut registers available for direct-in use or to register ripple output. ninth ff dedicated to ripple out, if used. the submodes of r ipple mode are adder/subtractor, counter, multiplier, and comparator. memory all luts and latches/ffs used to create a 32x4 synchronous dual-port ram. can be used as single-port or as rom. mode clk [1:0] lsr [1:0] ce [1:0] sel [1:0] logic clk to all latches/ ffs lsr to all latches/ffs, enabled per nibble and f or ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff select between lut input and direct input for eight latches/ffs half logic/ half ripple clk to all latches/ ffs lsr to all latches/ff, enabled per nibble and f or ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff select between lut input and direct input for eight latches/ffs ripple clk to all latches/ ffs lsr to all latches/ffs, enabled per nibble and f or ninth ff ce to all latches/ffs, selectable per nibble and for ninth ff select between lut input and direct input for eight latches/ffs memory (ram) clk to ram lsr0 port enable 2 ce1 ram write enable ce0 port enable 1 not used memory (rom) optional for synchronous outputs not used not used not used
lattice semiconductor 11 data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) logic mode the pfu diagram of figure 3 represents the logic mode of operation. in logic mode, the eight luts are used individually or in e xible groups to implement user logic functions. the latches/ffs may be used in con- junction with the luts or separately with the direct pfu data inputs. there are three basic submodes of lut operation in pfu logic mode: f4 mode, f5 mode, and the f6 mode. combinations of the submodes are possible in each pfu. f4 mode, shown simpli ed in figure 4, illustrates the uses of the basic 4-input luts in the pfu. the output of an f4 lut can be passed out of the pfu, captured at the luts associated latch/ff, or multiplexed with the adjacent f4 lut output using one of the f5[a:d] inputs to the pfu. only adjacent lut pairs (k 0 and k 1 , k 2 and k 3 , k 4 and k 5 , k 6 and k 7 ) can be multiplexed, and the output always goes to the even-numbered output of the pair. the f5 submode of the lut operation, shown simpli- ed in figure 4, indicates the use of 5-input luts to implement logic. 5-input luts are created from two 4-input luts and a multiplexer. the f5 lut is the same as the multiplexing of two f4 luts described previously with the constraint that the inputs to the f4 luts be the same. the f5[a:d] input is then used as the fth lut input. the equations for the two f4 luts will differ by the assumed value for the f5[a:d] input, one f4 lut assuming that the f5[a:d] input is zero, and the other assuming it is a one. the selection of the appropriate f4 lut output in the f5 mux by the f5[a:d] signal creates a 5-input lut. any combination of f4 and f5 luts is allowed per pfu using the eight 16-bit luts. examples are eight f4 luts, four f5 luts, and a combination of four f4 plus two f5 luts. tw o 6-input luts are created by shorting together the input of four 4-input luts (k0:3 and k4:7) which are m ultiplexed together. the f5 inputs of the adjacent f4 luts derive the fth and sixth inputs of the f6 mode. the f6 outputs, lut603 and lut647, are dedicated to the f6 mode or can be used as the outputs of mux8x1. mux8x1 modes are created by programming adjacent 4-input luts to 2x1 muxs and multiplexing down to create mux8x1. both f6 mode and mux8x1 are available in the upper and lower pfu nibbles. 5-9733(f) figure 4. simpli ed f4 and f5 logic modes k7_0 k7_1 k7_2 f5d lut4 lut4 2x1 mux f6 k7_3 k6_0 k6_1 k6_2 k6_3 k5_0 k5_1 k5_2 f5c lut4 lut4 2x1 mux f4 k5_3 k4_0 k4_1 k4_2 k4_3 k3_0 k3_1 k3_2 f5b lut4 lut4 2x1 mux f2 k3_3 k2_0 k2_1 k2_2 k2_3 k1_0 k1_1 k1_2 f5a lut4 lut4 2x1 mux f0 k1_3 k0_0 k0_1 k0_2 k0_3 k7 f7 k6 f6 k5 f5 k4 f4 k3 f3 k2 f2 k1 f1 k0 f0
12 12 lattice semiconductor data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) 5-9734(f)a figure 5. simpli ed f6 logic modes 5-9735(f) figure 6. mux 4x1 k7_0 k7_1 k7_2 k7_3 k6_0 k6_1 k6_2 k6_3 k5_0 k5_1 k5_2 k5_3 k4_0 k4_1 k4_2 k4_3 f5d f5c lut4 lut4 lut4 lut4 4x1 mux k3_0 k3_1 k3_2 k3_3 k2_0 k2_1 k2_2 k2_3 k1_0 k1_1 k1_2 k1_3 k0_0 k0_1 k0_2 k0_3 f5b f5a lut4 lut4 lut4 lut4 lut603 4x1 mux lut647 k7_0 k7_1 k7_2 f5d lut4 lut4 2x1 mux k6_0 k6_1 k6_2 f4 k5_0 k5_1 k5_2 f5c lut4 lut4 2x1 mux k4_0 k4_1 k4_2 f3 k3_0 k3_1 k3_2 f5b lut4 lut4 2x1 mux k2_0 k2_1 k2_2 f2 k1_0 k1_1 k1_2 f5a lut4 lut4 2x1 mux k0_0 k0_1 k0_2 f0
lattice semiconductor 13 data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) 5-9736(f)a figure 7. mux 8x1 softwired lut submode uses f4, f5 and f6 luts and internal pfu feedback routing to generate complex logic functions up to three lut-levels deep. multiplexers can be independently con gured to route certain lut outputs to the input of other luts. in this manner, very complex logic functions, some of up to 22 inputs, can be implemented in a single pfu at greatly enhanced speeds. it is important to note that an lut output that is fed back for softwired use is still available to be registered or output from the pfu. this means, for instance, that a logic equation that is needed by itself and as a term in a larger equa- tion need only be generated once, and plc routing resources will not be required to use it in the larger equation. k7_0 k7_1 k7_2 f5d lut4 lut4 k6_0 k6_1 k6_2 lut4 lut4 k5_0 k5_1 k5_2 k4_0 k4_1 k4_2 f5c lut4 k3_0 k3_1 k3_2 f5b lut4 lut4 k2_0 k2_1 k2_2 lut4 lut4 k1_0 k1_1 k1_2 k0_0 k0_1 k0_2 f5a lut4 mux8x1 4x1 mux 4x1 mux [lut647] mux8x1 [lut603]
14 lattice semiconductor data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) 5-5753(f) 5-5754(f) figure 8. softwired lut topology examples f4 f4 f4 f4 f4 f4 f4 f4 four 7-input functions in one pfu f5 f5 f5 f5 two 9-input functions in one pfu f5 f5 f5 f5 one 17-input function in one pfu f5 f5 f4 one 21-input function in one pfu f4 f4 f4 f4 f4 f4 f4 two 10-input functions in one pfu f4 f4 f4 f4 3 one of two 21-input functions in one pfu one 22-input function in one pfu f5 f6 f4 f4 f4 f4 f4 f5 4-input ? lut 5-input ? lut f6 6-input ? lut
lattice semiconductor 15 data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) half-logic mode series 4 fpgas are based upon a twin-quad architec- ture in the pfus. the byte-wide nature (eight luts, eight latches/ffs) may just as easily be viewed as two nibbles (two sets of four luts, four latches/ffs). the two nibbles of the pfu are organized so that any nib- b le-wide feature (excluding some softwired lut topolo- gies) can be swapped with any other nibble-wide f eature in another pfu. this provides for very e xible use of logic and for extremely e xible routing. the half- logic mode of the pfu takes advantage of the twin- quad architecture and allows half of a pfu, k [7:4] and associated latches/ffs, to be used in logic mode while the other half of the pfu, k [3:0] and associated latches/ffs, is used in ripple mode. in half-logic mode, the ninth ff may be used as a general-purpose ff or as a register in the ripple mode carry chain. ripple mode the pfu luts can be combined to do byte-wide ripple functions with high-speed carry logic. each lut has a dedicated carry-out net to route the carry to/from any adjacent lut. using the internal carry circuits, fast arithmetic, counter, and comparison functions can be implemented in one pfu. similarly, each pfu has carry-in (cin, fcin) and carry-out (cout, fcout) ports for fast-carry routing between adjacent pfus. the ripple mode is generally used in operations on two data buses. a single pfu can support an 8-bit ripple function. data buses of 4 bits and less can use the nibble-wide ripple chain that is available in half-logic mode. this nibble-wide ripple chain is also useful for longer ripple chains where the length modulo 8 is four or less. for example, a 12-bit adder (12 modulo 8 = 4) can be implemented in one pfu in ripple mode (8 bits) and one pfu in half-logic mode (4 bits), freeing half of a pfu for general logic mode functions. each lut has two operands and a ripple (generally carry) input, and provides a result and ripple (generally carry) output. a single bit is rippled from the previous lut and is used as input into the current lut. for lut k 0 , the ripple input is from the pfu cin or fcin port. the cin/fcin data can come from either the fast-carry routing (fcin) or the pfu input (cin), or it can be tied to logic 1 or logic 0. in the following discussions, the notations lut k 7 /k 3 and f[7:0]/f[3:0] are used to denote the lut that pro- vides the carry-out and the data outputs for full pfu r ipple operation (k 7 , f[7:0]) and half-logic ripple operation (k 3 , f[3:0]), respectively. the ripple mode diagram (figure 9) shows full pfu ripple operation, with half-logic ripple connections shown as dashed lines. the result output and ripple output are calculated by using generate/propagate circuitry. in ripple mode, the two operands are input into k z [1] and k z [0] of each lut. the result bits, one per lut, are f[7:0]/f[3:0] (see figure 9). the ripple output from lut k 7 /k 3 can be routed on dedicated carry circuitry into any of four adja- cent plcs, and it can be placed on the pfu cout/ fcout outputs. this allows the plcs to be cascaded in the ripple mode so that nibble-wide ripple functions can be expanded easily to any length. result outputs and the carry-out may optionally be reg- istered within the pfu. the capability to register the r ipple results, including the carry output, provides for improved counter performance and simpli ed pipelin- ing in arithmetic functions. 5-5755(f). figure 9. ripple mode f7 k 7 [1] k 7 [0] k7 dq c c dq q7 regout cout f6 k 6 [1] k 6 [0] k6 dq q6 f4 k 4 [1] k 4 [0] k4 dq q4 f3 k 3 [1] k 3 [0] k3 dq q3 f2 k 2 [1] k 2 [0] k2 dq q2 f1 k 1 [1] k 1 [0] k1 dq q1 f5 k 5 [1] k 5 [0] k5 dq q5 f0 k 0 [1] k 0 [0] k0 dq q0 cin/fcin fcout
16 16 lattice semiconductor data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) the ripple mode can be used in one of four submodes. the rst of these is adder-subtractor submode . in this submode, each lut generates three separate out- puts. one of the three outputs selects whether the carry-in is to be propagated to the carry-out of the cur- rent lut or if the carry-out needs to be generated. if the carry-out needs to be generated, this is provided by the second lut output. the result of this selection is placed on the carry-out signal, which is connected to the next lut carry-in or the cout/fcout signal, if it is the last lut (k 7 /k 3 ). both of these outputs can be any equation created from k z [1] and k z [0], but in this case, they have been set to the propagate and gener- ate functions. the third lut output creates the result bit for each lut output connected to f[7:0]/f[3:0]. if an adder/subtrac- tor is needed, the control signal to select addition or subtraction is input on f5a/f5c inputs. these inputs generate the controller input as. when as = 0 this function performs the adder, a + b. when as = 1 the function performs the subtractor, a ? b. the result bit is created in one-half of the lut from a single bit from each input bus k z [1:0], along with the ripple input bit. the second submode is the counter submode (see figure 10). the present count, which may be initialized via the pfu din inputs to the latches/ffs, is supplied to input k z [0], and then output f[7:0]/f[3:0] will either be incremented by one for an up counter or decre- mented by one for a down counter. if an up/down counter is needed, the control signal to select the direc- tion (up or down) is input on f5a and f5c. when f5[a:c], respectively per nibble, is a logic 1, this indi- cates a down counter and a logic 0 indicates an up counter. 5-5756(f) figure 10. counter submode f7 k 7 [0] k7 dq c c dq q7 regcout cout f6 k 6 [0] k6 dq q6 f4 k 4 [0] k4 dq q4 f3 k 3 [0] k3 dq q3 f2 k 2 [0] k2 dq q2 f1 k 1 [0] k1 dq q1 f5 k 5 [0] k5 dq q5 f0 k 0 [0] k0 dq q0 cin/fcin fcout
lattice semiconductor 17 data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) in the third submode, m ultiplier submode , a single pfu can affect an 8x1 bit (4x1 for half-ripple mode) m ultiply and sum with a partial product (see figure 11). the multiplier bit is input at f5[a:c], respectively per nibble, and the multiplicand bits are input at k z [1], where k 7 [1] is the most signi cant bit (msb). k z [0] con- tains the partial product (or other input to be summed) from a previous stage. if f5[a:c] is logical 1, the multi- plicand is added to the partial product. if f5[a:c] is log- ical 0, 0 is added to the partial product, which is the same as passing the partial product. cin/fcin can bring the carry-in from the less signi cant pfus if the m ultiplicand is wider than 8 bits, and cout/fcout holds any carry-out from the multiplication, which may then be used as part of the product or routed to another pfu in multiplier mode for multiplicand width expan- sion. ripple mode?s fourth submode features equality comparators. the functions that are explicitly available are a b, a b, and a b, where the value for a is input on k z [0], and the value for b is input on k z [1]. a v alue of 1 on the carry-out signals valid argument. for e xample, a carry-out equal to 1 in ab submode indi- cates that the value on k z [0] is greater than or equal to the value on k z [1]. conversely, the functions a b, a + b, and a > b are available using the same func- tions but with a 0 output expected. for example, a > b with a 0 output indicates a b. table 4 shows each function and the output expected. if larger than 8 bits, the carry-out signal can be cas- caded using fast-carry logic to the carry-in of any adja- cent pfu. the use of this submode could be shown using figure 9, except that the cin/fcin input for the least signi cant pfu is controlled via con guration. ta b le 4. ripple mode equality comparator functions and outputs 5-5757(f) key: c = con guration data. note: f5[a:c] shorted together figure 11. multiplier submode equality function isplever submode t rue, if carry-out is: a ba b1 a ba b1 a ba b1 a < b a b0 a > b a b0 a = b a b0 k7[1] k7[0] + d q c c dq 1 00 k7 f5[a:c] k4[1] k4[0] + d q 1 00 k4 k3[1] k3[0] + d q 1 00 k3 k2[1] k2[0] + d q 1 00 k2 k1[1] k1[0] + d q 1 00 k1 k6[1] k6[0] + d q 1 00 k6 k5[1] k5[0] + d q 1 00 k5 k0[1] k0[0] + d q 1 00 k0 q0 f0 q1 f1 q2 f2 q3 f3 q4 f4 q5 f5 q6 f6 q7 f7 cout regcout
18 lattice semiconductor data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) memory mode the series 4 pfu can be used to implement a 32x4 (128-bit) synchronous, dual-port ram). a block diagram of a pfu in memory mode is shown in figure 12. this ram can also be con gured to work as a single-port memory and because initial values can be loaded into the ram during con guration, it can also be used as a rom. 5-5969(f)a 1. clk[0:1] are commonly connected in memory mode. 2. ce1 = write enable = wren; wren = 0 (no write enable); wren = 1 (write enabled). ce0 = write port enable 0; ce0 = 0, wren = 0; ce0 = 1, wren = ce1. lsr0 = write port enable 1; lsr0 = 0, wren = ce0; lsr0 = 1, wren = ce1. figure 12. memory mode q6 q4 q2 q0 d 5 q cin(wa1) k z [3:0] 4 f5[a:d] d q din7(wa3) d q din5(wa2) d q din3(wa1) d q din1(wa0) d q din6(wd3) d q din4(wd2) d q din2(wd1) d q din0(wd0) d q ce0, lsr0 s/e clk[0:1] 4 write write read read 4 f6 f4 f2 f0 d q d q d q d q write ram clock address[4:0] address[4:0] data[3:0] data[3:0] enable (see note 2.) ce1
lattice semiconductor 19 data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) the pfu memory mode uses all luts and latches/ffs including the ninth ff in its implementation as shown in figure 12. the read address is input at the k z [3:0] and f5[a:d] inputs where k z [0] is the lsb and f5[a:d] is the msb, and the write address is input on cin (msb) and din[7, 5, 3, 1], with din[1] being the lsb. write data is input on din[6, 4, 2, 0], where din[6] is the msb, and read data is available combinatorially on f[6, 4, 2, 0] and registered on q[6, 4, 2, 0] with f[6] and q[6] being the msb. the write enable controlling ports are input on ce0, ce1, and lsr0. ce1 is the active- high write enable (ce1 = 1, ram is write enabled). the rst write port is enabled by ce0. the second write port is enabled with lsr0. the pfu clk (clk0) signal is used to synchronously write the data. the polarities of the clock, write enable, and port enables are all pro- gr ammable. write-port enables may be disabled if they are not to be used. data is written to the write data, write address, and write enable registers on the active edge of the clock, b ut data is not written into the ram until the next clock edge one-half cycle later. the read port is actually asynchronous, providing the user with read data very quickly after setting the read address, but timing is also provided so that the read port may be treated as fully synchronous for write then read applications. if the read and write address lines are tied together (main- taining msb to msb, etc.), then the dual-port ram operates as a synchronous single-port ram. if the write enable is disabled, and an initial memory contents is provided at con guration time, the memory acts as a r om (the write data and write address ports and write port enables are not used). wider memories can be created by operating two or more memory mode pfus in parallel, all with the same address and control signals, but each with a different nibble of data. to increase memory word depth above 32, two or more plcs can be used. figure 10 shows a 128x8 dual-port ram that is implemented in eight plcs. this gure demonstrates data path width expan- sion by placing two memories in parallel to achieve an 8-bit data path. depth expansion is applied to achieve 128 words deep using the 32-word deep pfu memo- r ies. in addition to the pfu in each plc, the slic (described in the next section) in each plc is used for read address decodes and 3-state drivers. the 128x8 ram shown could be made to operate as a single-port ram by tying (bit-for-bit) the read and write addresses. to achieve depth expansion, one or two of the write address bits (generally the msbs) are routed to the write port enables as in figure 10. for 2 bits, the bits select which 32-word bank of ram of the four available from a decode of two wpe inputs is to be written. simi- larly, 2 bits of the read address are decoded in the slic and are used to control the 3-state buffers through which the read data passes. the write data bus is common, with separate nibbles for width expansion, across all plcs, and the read data bus is common (again, with separate nibbles) to all plcs at the output of the 3-state buffers. figure 13 also shows the capability to provide a read enable for rams/roms using the slic cell. the read enable will 3-state the read data bus when inactive, allowing the write data and read data buses to be tied together if desired.
20 lattice semiconductor data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) 5-5749(f) figure 13. memory mode expansion example?128x8 ram rd[7:0] we wa[6:0] ra[6:0] clk wa ra wpe 1 wpe 2 we wd[7:4] 5 5 4 plc 8 wd[7:0] 8 7 7 wa ra wpe 1 wpe 2 we rd[3:0] wd[3:0] 5 5 4 plc rd[7:4] wa ra wpe 1 wpe 2 we wd[7:4] 5 5 4 plc wa ra wpe 1 wpe 2 we rd[3:0] wd[3:0] 5 5 4 plc rd[7:4] re re 4 re 4 re 4 re 4 supplemental logic and interconnect cell each plc contains a slic embedded within the plc routing, outside of the pfu. as its name indicates, the slic performs both logic and interconnect (routing) functions. its main features are 3-statable, bidirectional b uffers, and a pa l -like decoder capability. figure 14 shows a diagram of a slic with all of its features shown. all modes of the slic are not available at one time. the ten slic inputs can be sourced directly from the pfu or from the general routing fabric. si[0:9] inputs can come from the horizontal or vertical routing and i[0:9} comes from the pfu outputs o[9:0]. these inputs can also be tied to a logical 1 or 0 constant. the inputs are twin-quad in nature and are segregated into two g roups of four nibbles and a third group of two inputs f or control. each input nibble groups also have 3-state capability, however the third pair does not. there is one 3-state control (tri) for each slic, with the capability to invert or disable the 3-state control for each group of four bidis. separate 3-state control for each nibble-wide group is achievable by using the slics decoder (dec) output, driven by the group of two bidis, to control the 3-state of one bidi nibble while using the tri signal to control the 3-state of the other bidi nibble. figure 15 shows the slic in buffer mode with available 3-state control from the tri and dec signals. if the entire slic is acting in a buffer capacity, the dec output may be used to generate a constant logic 1 (v hi ) or logic 0 (v lo ) signal for general use. the slic may also be used to generate pa l -like and- or with optional invert (aoi) functions or a decoder of up to 10 bits. each group of buffers can feed into an and gate (4-input and for the nibble groups and 2-input and for the other two buffers). these and gates then feed into a 3-input gate that can be con g- ured as either an and gate or an or gate. the output of the 3-input gate is invertible and is output at the dec output of the slic. figure 19 shows the slic in full decoder mode. the functionality of the slic is parsed by the two nib- b le-wide groups and the 2-bit buffer group. each of these groups may operate independently as bidi buff- ers (with or without 3-state capability for the nibble- wide groups) or as a pa l /decoder.
lattice semiconductor 21 data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) as discussed in the memory mode section, if the slic is placed into one of the modes where it contains both b uffers and a decode or aoi function (e.g., b uf_buf_dec mode), the dec output can be gated with the 3-state input signal. this allows up to a 6-input decode (e.g., buf_dec_dec mode) plus the 3-state input to control the enable/disable of up to four buffers per slic figure 15?figure 19 show several con gura- tions of the slic, while table 5 shows all of the possi- b le modes. ta b le 5. slic modes 5-5744(f).a. figure 14. slic all modes diagram mode no. mode buf [3:0] buf [7:4] buf [9:8] 1b uffer buffer buffer buffer 2b uf_buf_dec buffer buffer decoder 3b uf_dec_buf buffer decoder buffer 4 b uf_dec_dec buffer decoder decoder 5 dec_buf_buf decoder buffer buffer 6 dec_buf_dec decoder buffer decoder 7 dec_dec_buf decoder decoder buffer 8 decoder decoder decoder decoder sin9 i9 sout09 dec dec 0/1 0/1 tri 0/1 0/1 sout08 sout07 sout06 sout05 sout04 sout03 sout02 sout01 sout00 logic 1 or 0 sin8 i8 logic 1 or 0 sin7 i7 logic 1 or 0 sin6 i6 logic 1 or 0 sin5 i5 logic 1 or 0 sin4 i4 logic 1 or 0 sin3 i3 logic 1 or 0 sin2 i2 logic 1 or 0 sin1 i1 logic 1 or 0 sin0 i0 logic 1 or 0
22 lattice semiconductor data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) 5-5745(f).a figure 15. buffer mode 5-5746(f).a figure 16. buffer-buffer-decoder mode sout08 tri 0/1 0/1 1 0 dec this can be used to generate a vhi or vlo sin8 i8 logic 1 or 0 sout09 sin9 i9 logic 1 or 0 sout07 sin7 i7 logic 1 or 0 sout06 sin6 i6 logic 1 or 0 sout05 sin5 i5 logic 1 or 0 sout04 sin4 i4 logic 1 or 0 sout03 sin3 i3 logic 1 or 0 sout02 sin2 i2 logic 1 or 0 sout01 sin1 i1 logic 1 or 0 sout00 sin0 i0 logic 1 or 0 tri dec 1 1 1 1 sout07 sin7 i7 logic 1 or 0 sout06 sin6 i6 logic 1 or 0 sout05 sin5 i5 logic 1 or 0 sout04 sin4 i4 logic 1 or 0 sin9 i9 logic 1 or 0 sin8 i8 logic 1 or 0 sout03 sin3 i3 logic 1 or 0 sout02 sin2 i2 logic 1 or 0 sout01 sin1 i1 logic 1 or 0 sout00 sin0 i0 logic 1 or 0
lattice semiconductor 23 data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) 5-5747(f).a figure 17. buffer-decoder-buffer mode 5-5750(f) figure 18. buffer-decoder-decoder mode tri dec 1 1 sout08 sin8 i8 logic 1 or 0 sout09 sin9 i9 logic 1 or 0 sin7 logic 1 or 0 sin6 logic 1 or 0 sin5 logic 1 or 0 sin4 logic 1 or 0 sout03 sin3 i3 logic 1 or 0 sout02 sin2 i2 logic 1 or 0 sout01 sin1 i1 logic 1 or 0 sout00 sin0 i0 logic 1 or 0 if low then 3 state buffers are high z dec tri 1 1 sin7 logic 1 or 0 sin6 logic 1 or 0 sin5 logic 1 or 0 sin4 logic 1 or 0 sout03 sin3 i3 logic 1 or 0 sout02 sin2 i2 logic 1 or 0 sout01 sin1 i1 logic 1 or 0 sout00 sin0 i0 logic 1 or 0 sin9 logic 1 or 0 sin8 logic 1 or 0
24 24 lattice semiconductor data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) 5-5748(f) figure 19. decoder mode plc latches/flip-flops the eight general-purpose latches/ffs in the pfu can be used in a variety of con gurations. in some cases, the con guration options apply to all eight latches/ffs in the pfu and some apply to the latches/ffs on a nib- b le-wide basis where the ninth ff is considered inde- pendently. for other options, each latch/ff is independently programmable. in addition, the ninth ff can be used for a variety of functions. ta b le 6 summarizes these latch/ff options. the latches/ffs can be con gured as either positive- or negative-level sensitive latches, or positive or negative edge-triggered ffs (the ninth register can only be a ff). all latches/ffs in a given pfu share the same clock, and the clock to these latches/ffs can be inverted. the input into each latch/ff is from either the corresponding lut output (f[7:0]) or the direct data input (din[7:0]). the latch/ff input can also be tied to logic 1 or to logic 0, which is the default. tab le 6. con guration ram controlled latch/ flip-flop operation each pfu has two independent programmable clocks, clock enable ce[1:0], local set/reset lsr[1:0], and front end data selects sel[1:0]. when ce is disabled, each latch/ff retains its previous value when clocked. the clock enable, lsr, and sel inputs can be inverted to be active-low. dec sin7 logic 1 or 0 sin6 logic 1 or 0 sin5 logic 1 or 0 sin4 logic 1 or 0 sin9 logic 1 or 0 sin8 logic 1 or 0 sin3 logic 1 or 0 sin1 logic 1 or 0 sin2 logic 1 or 0 sin0 logic 1 or 0 function options common to all latches/ffs in pfu lsr operation asynchronous or synchronous. clock polarity noninverted or inverted. f ront-end select* direct (din[7:0]) or from lut (f[7:0]). lsr priority either lsr or ce has priority. latch/ff mode latch or ff. enable gsrn gsrn enabled or has no effect on pfu latches/ffs. set individually in each latch/ff in pfu set/reset mode set or reset. by group (latch/ff[3:0], latch/ff[7:4], and ff[8]) clock enable ce or none. lsr control lsr or none. * not available for ff[8].
lattice semiconductor 25 data sheet november, 2002 orca series 4 fpgas programmable logic cells (continued) the set/reset operation of the latch/ff is controlled by two parameters: reset mode and set/reset value. when the gsrn and local set/reset (lsr) signals are not asserted, the latch/ff operates normally. the reset mode is used to select a synchronous or asynchronous lsr operation. if synchronous, lsr has the option to be enabled only if clock enable (ce) is active or for lsr to have priority over the clock enable input, thereby set- ting/resetting the ff independent of the state of the clock enable. the clock enable is supported on ffs, not latches. it is implemented by using a 2-input multiplexer on the ff input, with one input being the previous state of the ff and the other input being the new data applied to the ff. the select of this 2-input multiplexer is clock enable (ce), which selects either the new data or the previous state. when the clock enable is inactive, the ff output does not change when the clock edge arrives. the gsrn signal is only asynchronous, and it sets/ resets all latches/ffs in the fpga based upon the set/ reset con guration bit for each latch/ff. the set/reset v alue determines whether gsrn and lsr are set or reset inputs. the set/reset value is independent for each latch/ff. an option is available to disable the gsrn function per pfu after initial device con gura- tion. the latch/ff can be con gured to have a data front- end select. two data inputs are possible in the front-end select mode, with the sel signal used to select which data input is used. the data input into each latch/ff is from the output of its associated lut, f[7:0], or direct from din[7:0], bypassing the lut. in the front-end data select mode, both signals are avail- able to the latches/ffs. if either or both of these inputs is unused or is unavail- able, the latch/ff data input can be tied to a logic 0 or logic 1 instead (the default is logic 0). the latches/ffs can be con gured in three basic modes: local synchronous set/reset: the input into the pfu?s lsr port is used to synchronously set or reset each latch/ff. local asynchronous set/reset: the input into lsr asynchronously sets or resets each latch/ff. latch/ff with front-end select, lsr either synchro- nous or asynchronous: the data select signal selects the input into the latches/ffs between the lut out- put and direct data in. f or all three modes, each latch/ff can be indepen- dently programmed as either set or reset. figure 20 provides the logic functionality of the front-end select, global set/reset, and local set/reset operations. the ninth pfu ff, which is generally associated with registering the carry-out signal in ripple mode func- tions, can be used as a general-purpose ff. it is only an ff and is not capable of being con gured as a latch. because the ninth ff is not associated with an lut, there is no front-end data select. the data input to the ninth ff is limited to the cin input, logic 1, logic 0, or the carry-out in ripple and half-logic modes. 5-9737(f).a key: c = con guration data. figure 20. latch/ff set/reset con gurations ce ce dq s_set s_reset clk set reset f din logic 1 logic 0 lsr cd gsrn ce ce dq clk set reset f din logic 1 logic 0 cd gsrn lsr ce ce dq clk set reset f din logic 1 logic 0 cd gsrn lsr din sel
26 26 lattice semiconductor data sheet november, 2002 orca series 4 fpgas embedded block ram (ebr) the orca series 4 devices compliment the distributed pfu ram with large blocks of memory macrocells. the memory is available in 512 words by 18 bits/word b locks with 2 read and 2 write ports with two byte lane enables which operate with quad-port functionality. additional logic has been incorporated for fifo, multi- plier, and cam implementations. the ram blocks are organized along the plc rows and are added in pro- portion to the fpga array sizes as shown in table 7. the contents of the ram blocks may be optionally ini- tialized during fpga con guration. tab le 7. orca series 4? available embedded block ram each highly e xible 512x18 (quad-port, two read/two write) ram block can be programmed by the user to meet their particular function. each of the ebr con gu- r ations use the physical signals as shown in ta b le 8. quad-port addressing permits simultaneous read and write operations on all four ports. the ebr ports are written synchronously on the posi- tive-edge of ckw. synchronous read operations uses the positive-edge of ckr. options are available to use synchronous read address registers and read output registers, or to bypass these registers and have the ram read operate asynchronously. detailed informa- tion about the ebr blocks is found in various applica- tion notes. isplever provides scuba as a ram generation tool f or ebr rams. many of the ebr sub-modes are sup- ported and the initialization values can also be de ned. ebr features quad port ram modes (two read/two write) one 512 x 18 ram with optional built-in write arbitra- tion. one 1024 x 18 ram built on two blocks with built-in decode logic for simpli ed implementation. dual port ram modes (one read/one write) one 256 x 36 ram. one 1k x 9 ram. tw o independent 512 x 9 rams built in one ebr with separate read clocks, write clocks and enables. tw o independent rams with arbitrary number of w ords whose sum is 512 words or less by 18 bits/ w ord or less. the joining of ram blocks is supported to create wider deeper memories. the adjacent routing interface pro- vided by the cibs allow the cascading of blocks together with minimal penalties due to routing delays. it is also possible to connect any or all of the ebr ram b locks together through the embedded system bus, which is discussed in a later section of this data sheet. arbitration logic is optionally programmed by the user to signal occurrences of data collisions as well as to b lock both ports from writing at the same time. the arbitration logic prioritizes port1. when utilizing the arbiter, the signal busy indicates data is being written to port1. this busy output signals port1 activity by driving a high output. if the arbiter is turned off both ports could be written at the same time and the data w ould be corrupt. in this scenario the busy signal will indicate a possible error. there is also a user option which dedicates port 1 to communications to the system bus. in this mode the user logic only has access to port0 and arbitration logic is enabled. the system bus utilizes the priority given to it by the arbiter therefore the system bus will always be able to write to the ebr. device number of blocks number of ebr bits or4e02 8 74k or4e04 12 111k or4e06 16 147k
lattice semiconductor 27 data sheet november, 2002 orca series 4 fpgas embedded block ram (ebr) (continued) fifo modes fifos can be con gured to 256, 512, or 1k depths and 36, 18, or 9 widths respectively but also can be e xpanded using multiple blocks. fifo works synchro- nously with the same read and write clock where the read port can be registered on the output or not regis- tered. it can also be optionally con gured asynchro- nously with different read and write clocks and the same read port register options. integrated ags allow the user the ability to fully utilize the ebr for fifo, without the need to dedicate an address for providing distinct full/empty status. there are four programmable ags provided for each fifo: empty, partially empty, full, and partially full fifo sta- tus. the partially empty and partially full ags are pro- gr ammable with the e xibility to program the ags to any value from the full or empty threshold. the pro- gr ammed values can be set to a x ed value through the bitstream or a dynamic value can be controlled by input pins of the ebr fifo. when the fifo is in asynchro- nous mode, the fifo ags use grey code counters to ensure proper glitch-free operation. multiplier modes the orca series 4 ebr supports two variations of m ultiplier functions. constant coef cient multiply [kcm] mode will produce a 24-bit output of a x ed 8-bit constant multiply of a 16-bit number or a x ed 16-bit constant multiply of an 8-bit number. this kcm multi- plies a constant times a 16- or 8-bit number and pro- duces a product as a 24-bit result. the coef cient and m ultiplication tables are stored in memory. the input can be con gured to be registered for pipelining. both write ports are available during multiply mode so that the user logic can update and modify the coef - cients for dynamic coef cient updates. the scuba program in isplever should be used to create the kcm multipliers, including the input of initial coef - cients. an 8 x 8 multiply mode is con gurable to either a pipelined or combinatorial multiplier function of two 8- bit numbers. two 8-bit operands are multiplied to yield a 16-bit product. the input can be registered in pipeline mode. cam mode the cam block is a binary content address memory that provides fast address searches by receiving data input and returning addresses that contain the data. implemented in each ebr are two 16-word x 8-bit cam function blocks. the cam has three modes, single match, multiple match and clear, which are all achieved in one clock cycle. in single match mode, a 8-bit data input is inter- nally decoded and reports a match when data is present in a particular ram address. its result is reported by a corresponding single address bit. in mul- tiple match the same occurs with the exception of multi- ple address lines report the match. clear mode is used to clear the cam contents by erasing all locations one cycle per location. the ebr blocks in cam mode may be cascaded to produce larger cams.
28 lattice semiconductor data sheet november, 2002 orca series 4 fpgas embedded block ram (ebr) (continued) ta b le 8. ram signals po rt signals i/o function port 0 ar0[#:0] i address to be read (variable width depending on ram size). a w0[#:0] i address to be written (variable width depending on ram size). bw0<1:0> i byte-write enable. byte = 8-bits + parity bit. <1> = bits[17, 15:9] <0> = bits[16, 7:0] ckr0 i positive-edge asynchronous read clock. ckw0 i positive-edge synchronous write clock. csr0 i enables read to output. active high. csw0 i enables write to output. active high. d [#:0] i input data to be written to ram (variable width depending on ram size). q [#:0] o output data of memory contents at referenced address (variable width depending on ram size). port 1 ar1[#:0] i address to be read (variable width depending on ram size). a w1[#:0] i address to be written (variable width depending on ram size). bw1<1:0> i byte-write enable. byte = 8-bits + parity bit. <1> = bits[17, 15:9] <0> = bits[16, 7:0] ckr1 i positive-edge asynchronous read clock. ckw1 i positive-edge synchronous write clock. csr1 i enables read to output. active high. csw1 i enables write to output. active high. d [#:0] i input data to be written to ram (variable width depending on ram size). q [#:0] o output data of memory contents at referenced address (variable width depending on ram size). control b usy o port1 writing. active high. reset i data output registers cleared. memory contents unaffected. active-low.
lattice semiconductor 29 data sheet november, 2002 orca series 4 fpgas embedded block ram (continued) 0308(f) figure 21. ebr read and write cycles with write through and nonregistered read port ta b le 9. fifo signals po rt signals i/o function ar0[5:0] i programs fifo ags. used for partially empty ag size. ar1[9:0] i programs fifo ags. used for partially full ag size. ff o full flag. pff o partially full flag. pef o partially empty flag. ef o empty flag. d0[17:0] i data inputs for all con gurations. d1[17:0] i data inputs for 256x36 con gurations only. ckw[0:1] i positive-edge write port clock. port 1 only used for 256x36 con gurations. ckr[0:1] i positive-edge read port clock. port 1 only used for 256x36 con gurations. csw[1:0] i active-high write enable. port 1 only used for 256x36 con gurations. csr[1:0] i active-high read enable. port 1 only used for 256x36 con gurations. reset i active-low resets fifo pointers. q0[17:0] o data outputs for all con gurations. q1[17:0] o data outputs for 256x36 con gurations. ckwph ckwpl cswsu cswh awh dsu dh bwsu bwh awsu ckwq aq aqh abcd bc a d c ckw csw aw d bw ar q
30 lattice semiconductor data sheet november, 2002 orca series 4 fpgas embedded block ram (continued) ta b le 10. constant multiplier signals ta b le 11. 8x8 multiplier signals ta b le 12. cam signals po rt signals i/o function ar0[15:0] i data input?operand. a w(1:0)[8:0] i address bits. d(1:0)[17:0] i data inputs to load memory or change coef cient. ckw[0:1] i positive-edge write port clock. ckr[0:1] i positive-edge read port clock. used for synchronous multiply mode. csw[1:0] i active-high write enable. csr[1:0] i active-high read enable. q[23:0] o data outputs?product result. po rt signals i/o function ar0[7:0] i data input-multiplicand. ar1[7:0] i data input-multiplier. ckr[0:1] i positive-edge read port clock. used for synchronous multiply mode. csr[1:0] i active-high read enable. q[15:0] o data outputs-product. po rt signals i/o function ar(1:0)[7:0] i data match. a w(1:0)[8:0] i data write. d(1:0)[17] i clear data active high. d(1:0)[16] i single match active high. d(1:0)[3:0] i cam address for data write. csw[1:0] i active-high write enable. enable for cam data write. csr[1:0] i active-high read enable. enable for cam data match. q(1:0)15:0] o decoded data outputs. ?1? corresponds to a data match at that address location.
lattice semiconductor 31 data sheet november, 2002 orca series 4 fpgas routing resources the abundant routing resources of the series 4 archi- tecture are organized to route signals individually or as b uses with related control signals. both local and glo- bal signals utilize high-speed buffered and nonbuffered routes. one plc segmented (x1), six plc segmented (x6), and bused half chip (xhl) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. x1 routes cross width of one plc and provide local connectivity to pfu and slic inputs and outputs. x6 lines cross width of 6 plcs and are unidirectional and b uffered with taps in the middle and on the end. seg- ments allow connectivity to pfu/slic outputs (driven at one end-point), other x6 lines (at end-points), and x1 lines for access to pfu/slic inputs. xh lines run ve r tically and horizontally the distance of half the device and are useful for driving medium/long distance 3-state routing. the improved routing resources offer great e xibility in moving signals to and from the logic core. this e xibil- ity translates into an improved capability to route designs at the required speeds even when the i/o sig- nals have been locked to speci c pins. the buffered routing capability also allows a very large fanout to be driven from each logic output, thus greatly reducing the amount of logic replication required by synthetic tools. generally, the isplever development system is used to automatically route interconnections. interactive routing with the isplever design editor (epic) is also av ailable for design optimization. the routing resources consist of switching circuitry and metal interconnect segments. generally, the metal lines which carry the signals are designated as routing segments. the switching circuitry connects the routing segments, providing one or more of three basic func- tions: signal switching, ampli cation, and isolation. a net running from a pfu, ebr, or pio output (source) to a plc, ebr, or pio input (destination) consists of one or more routing segments, connected by switching cir- cuitry called con gurable interconnect points (cips). clock distribution network clock distribution is made up of three types of clock networks: primary, secondary, and edge clocks. these are described below and more information is available in the series 4 clocking strategies application note. global primary clock nets the series 4 fpgas provide eight fully distributed glo- bal primary clock net routing resources. the scheme dedicates four of the eight resources to provide fast pri- mary nets and four are available for general primary nets. the fast primary nets are targeted toward low- skew and small injection times while the general pri- mary nets are also targeted toward low-skew but have more source connection e xibility. fast access to the global primary nets can be sourced from two pairs of pads located in the center of each side of the device, from the programmable plls and dedicated network plls located in the corners, or from general routing at the center of the device or at the middle of any side of the device. the i/o pads are semi-dedicated in pairs for use of differential i/o clocking or single-ended i/o clock sources. however if these pads are not needed to source the clock network they can be utilized for gen- eral i/o. the clock routing scheme is patterned using ve r tical and horizontal routes which provide connectiv- ity to all plc columns. secondary clock and control nets secondary clock control and routing provides e xible clocking and control signalling for local regions. since secondary nets usually have high fanouts and require low skew, the series 4 devices utilize a spine and branch that uses x6 segments with high-speed connec- tions provided from the spines to the branches. the branches then have high-speed connections to plc, pio, and ebr clock and control signals. this strategy provides a e xible connectivity and routes can be sourced from any i/o pin, all plls, or from plc or ebr logic. secondary edge clock nets and fast edge clock nets six secondary edge clock nets per side are distributed around the edges of the device and are available for ev ery pio. all pios and plls can drive the secondary edge clocks and are used in conjunction with the sec- ondary spines discussed above to drive the same edge clock signal into the internal logic array. the edge sec- ondary clocks provide fast injection to the plc array and i/o registers. one of the six secondary edge clocks provided per side of the device is a special fast edge clock net that only clocks input registers for fur- ther reduced setup/hold times.this timing path can only be driven from one of the four pio input pins in each pic.
32 32 lattice semiconductor data sheet november, 2002 orca series 4 fpgas routing resources (continued) cycle stealing a new feature in series 4 fpgas is the ability to steal time from one register-to-register path and use that time in either the previous path before the rst register or in a later path after the last register. this is done through selectable clock delays for every plc register, ebr register, and pio register. there are four pro- gr ammable delay settings, including the default zero added delay value. this allows performance increases on typical critical paths from 15% to 40%. isplever includes software to automatically take advantage of this capability to increase overall system speed. this is done after place and route is completed and uses tim- ing driven algorithms based on the customer?s prefer- ence le. a hold time check is also performed to verify no minimum hold time issues are introduced. more information on this clocking feature, including how it can be used to improve device setup times, hold times, clock-to-out delays and can reduce ground bounce caused by switching outputs can be found in the cycle stealing application note. programmable input/output cells (pic) programmable i/o the series 4 programmable i/o addresses the demand f or the e xibility to select i/o that meets system inter- f ace requirements. i/os can be programmed in the same manner as in previous orca devices with the addition of new features which allow the user the e xi- bility to select new i/o types that support high-speed interfaces. each pic contains up to four programmable i/o (pio) pads and are interfaced through a common interface b lock (cib) to the fpga array. the pic is split into two pairs of i/o pads with each pair having independent clocks, clock enables, local set/reset, and global set/reset enable/disable. on the input side, each pio contains a programmable latch/ff which enables very fast latching of data from any pad. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input sig- nal, such as a multiplexed address/data signal, and register the signals without explicitly building a demulti- plexer with a pfu. on the output side of each pio, an output from the plc array can be routed to each output ff, and logic can be associated with each i/o pad. the output logic associ- ated with each pad allows for multiplexing of output sig- nals and other functions of two output signals. the output ff, in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the out- put buffer signal can be inverted, and the 3-state con- trol can be made active-high, active-low, or always enabled. in addition, this 3-state signal can be regis- tered or nonregistered. the series 4 i/o logic has been enhanced to include modes for high-speed uplink and downlink capabilities. these modes are supported through shift register logic which divides down incoming data or multiplies up out- going data. this new logic block also supports high- speed ddr mode requirements where data is clocked into and out of the i/o buffers on both edges of the clock. the new programmable i/o cell allows designers to select i/os which meet many new communication stan- dards permitting the device to hook up directly without any external interface translation. they support tradi- tional fpga standards as well as high-speed single- ended and differential pair signaling (as shown in ta b le 13). based on a programmable, bank-oriented i/o ring architecture, designs can be implemented using 3.3 v, 2.5 v, 1.8 v, and 1.5 v i/o levels. the i/o on the or4exx series devices allows compli- ance with pci local bus (rev. 2.2) 3.3 v signaling envi- ronments. the signaling environment used for each input buffer can be selected on a per-pin basis. the selection provides the appropriate i/o clamping diodes f or pci compliance. more information on the series 4 programmable i/o structure is available in the various application notes.
lattice semiconductor 33 data sheet november, 2002 orca series 4 fpgas programmable input/output cells (continued) ta b le 13. series 4 programmable i/o standards note: interfaces to ddr and zbt memories are supported through the interface standards shown above. the pios are located along the perimeter of the device. the pio name is represented by a two-letter designation to indicate the side of the device on which it is located followed by a number to indicate the row or column in which it is located. the rst letter, p, designates that the cell is a pio and not a plc. the second letter indicates the side of the array where the pio is located. the four sides are left (l), right (r), top (t), and bottom (b). a number follows to indicate the pic row or column. the individual i/o pad is indicated by a single letter (either a, b, c, or d) placed at the end of the pio name. as an example, pl10a indicates a pad located on the left side of the array in the tenth row. each pic interfaces to four bond pads through four pios and contains the necessary routing resources to provide an interface between i/o pads and the cibs. each pic contains input buffers, output buffers, routing resources, latches/ffs, and logic and can be con gured as an input, output, or bidirectional i/o. any pio is capable of sup- porting the i/o standards listed in table 13. the cibs that connect to the pics have signi cant local routing resources, similar to routing in the plcs. this new routing increases the ability to x user pinouts prior to placement and routing of a design and still maintain routabil- ity. the e xibility provided by the routing also provides for increased signal speed due to a greater variety of optimal signal paths. included in the routing interface is a fast path from the input pins to the pfu logic. this feature allows for input sig- nals to be very quickly processed by the slic decoder function and used on-chip or sent back off of the fpga. a diagram of a single pio is shown in figure 22, and table 14 provides an overview of the programmable functions in an i/o cell. standard v dd io (v) v ref (v) interface usage l vttl 3.3 na general purpose. l vcmos2 2.5 na l vcmos18 1.8 na pci 3.3 na pci. l vds 2.5 na point to point and multi-drop backplanes, high noise immunity. bused-lvds 2.5 na network backplanes, high noise immunity, bus architecture backplanes. l vpecl 3.3 na network backplanes, differential 100 mhz+ clocking, optical transceiver, high-speed networking. pecl 3.3 2.0 backplanes. gtl 3.3 0.8 backplane or processor interface. gtl+ 3.3 1.0 hstl-class i 1.5 0.75 high-speed sram and networking interfaces. htsl-class iii and iv 1.5 0.9 sttl3-class i and ii 3.3 1.5 synchronous dram interface. sstl2-class i and ii 2.5 1.25
34 lattice semiconductor data sheet november, 2002 orca series 4 fpgas programmable input/output cells (continued) 5-9732(f) figure 22. series 4 pio image from isplever design software outsh outddmux outdd outffmux outff clk4mux ec sc ce lsrmux lsr gsr enabled disabled srmode ce_over_lsr lsr_over_ce async cemux0 outdd clk outsh clk outdd outreg outreg do ck sp lsr and nand or nor xor xnor plogic pmux outshmux bufmode slew fast levelmode pci sstl2 sstl3 hstl1 hstl3 gtl gtlplus pecl lvpecl lvds p2mux outdd tsmux usrts tsreg do ck lsr reset set pullmode up down none inmux cemuxi normal inverted latchff d0 d1 ck sp lsr d0 ck latchff latch ff inddmux indd inck inff reset set reset set 1 0 0 0 0 1 ec sc delay iopad outmux cell ce 1 lvcmos2 lvcmos18 del0 del1 del2 del3 del0 del1 del2 del3 milliamps six twelve twentyfour resistor off on keepermode off on latch ff output side input side lvttl na na na lvds fast input
lattice semiconductor 35 data sheet november, 2002 orca series 4 fpgas programmable input/output cells (continued) inputs there are many major options on the pio inputs that can be selected in the isplever tools listed in table 14. inputs may have a pull-up or pull-down resistor selected on an input for signal stabilization and power management. input signals in a pio are passed to cib routing and/or a fast route into the clock routing sys- tem. a fast input from one pio per pic is also available to drive the edge clock network for fast i/o timing to other nearby pios. there is also a programmable delay available on the input. when enabled, this delay affects the inff and indd signals of each pio, but not the clock input. the delay allows any signal to have a guaranteed zero hold time when input. inputs should have transition times of less than 100 ns and should not be left oating. for full swing inputs, the timing characterization is done for rise/fall times of 1 v/ns. if any pin is not used, it is 3-stated with an internal pull-up resistor enabled automatically after con guration. floating inputs increase power con- sumption, produce oscillations, and increase system noise. the inputs in lvttl, lvcmos2, and l vcmos18 modes have a typical hysteresis of approx- imately 250 mv to reduce sensitivity to input noise. the pic contains input circuitry which provides protection against latch-up and electrostatic discharge. the other features of the pio inputs relate to the latch/ ff structure in the input path. in latch mode, the input signal is fed to a latch that is clocked by either the pri- mary, secondary, or edge clock signal. the clock may be inverted or noninverted. there is also a local set/ reset signal to the latch. the senses of these signals are also programmable as well as the capability to enable or disable the global set/reset signal and select the set/reset priority. the same control signals may also be used to control the input latch/ff when it is con gured as a ff instead of a latch, with the addition of another control signal used as a clock enable. the pios are paired together and have independent ce, set/reset, and gsrn control signals per pio pair. there are two options for zero-hold input capture in the pio. if input delay mode is selected to delay the signal from the input pin, data can be either registered or latched with guaranteed zero-hold time in the pio using a global primary system clock. the fast zero-hold mode of the pio input takes advantage of a latch/ff combination to latch the data quickly for zero-hold using a fast edge clock before passing the data to the ff which is clocked by a global primary system clock. the combination of input register capability with non- registered inputs provides for input signal demultiplex- ing without any additional resources. the pio input signal is sent to both the input register and directly to the unregistered input (indd). the signal is latched and output to routing at inff. these signals may then be registered or otherwise processed in the plcs. every pio input can also perform input double data r ate (ddr) functions with no plc resources required. this type of scheme is necessary for ddr applications which require data to be clocked in from the i/o on both edges of the clock. in this scheme the input of inff and insh are captured on the positive and negative edges of the clock. ta b le 14. pio options input option input ? speed fast, ? delayed, ? normal float ? v alue pull-up, ? pull-down, ? none register ? mode latch, ? ff, ? fast ? zero ? hold ? ff, ? none ? (direct ? input) clock ? sense inverted, ? noninverted keeper ? mode on, ? off l vds ? resistor on, ? off output option output ? speed fast, ? slew output ? drive ? current 12 ? ma/6 ? ma, ? 6 ? ma/3 ? ma, ? or 24 ? ma/12 ? ma output ? function ? normal, ? fast ? open ? drain output ? sense active-high, ? active-low 3-state ? sense active-high, ? active-low clock ? sense inverted, ? noninverted logic options see table 15 i/o ? controls option clock ? enable ? active-high, ? active-low, ? always ? enabled set/reset ? level active-high, ? active-low, ? no ? local ? reset set/reset ? t ype synchronous, ? asynchronous set/reset ? priority ce ? over ? lsr, ? lsr ? over ? ce gsr ? control enable ? gsr, ? disable ? gsr
36 36 lattice semiconductor data sheet november, 2002 orca series 4 fpgas programmable input/output cells (continued) outputs the pio?s output drivers have programmable drive capability and slew rates. two propagation delays (fast, slewlim) are available on output drivers. there are three combinations of programmable drive currents (24 ma sink/12 ma source, 12 ma sink/6 ma source, and 6 ma sink/3 ma source). at powerup, the output drivers are in slewlim mode with 12ma sink/6 ma source. if an output is not to be driven in the selected con guration mode, it is 3-stated with a pullup resistor. the output buffer signal can be inverted, and the 3-state control signal can be made active-high, active- low, or always enabled. in addition, this 3-state signal can be registered or nonregistered. additionally, there is a fast, open-drain output option that directly connects the output signal to the 3-state control, allowing the out- put buffer to either drive to a logic 0 or 3-state, but never to drive to a logic 1. every pio output can perform output data multiplexing with no plc resources required. this type of scheme is necessary for ddr applications which require data clocking out of the i/o on both edges of the clock. in this scheme the outff and outsh are registered and sent out on both the positive and negative edges of the clock using an output multiplexor. this multiplexor is controlled by either the edge clock or system clock. this multiplexor can also be con gured to select between one registered output from outff and one nonregistered output from outdd. the pic logic block can also generate logic functions based on the signals on the outdd and clk ports of the pio. the functions are and, nand, or, nor, xor, and xnor. table 15 is provided as a summary of the pio logic options. tab le 15. pio ? logic ? options pio register control signals the pio latches/ffs have various clock, clock enable (ce), local set/reset (lsr), and gsrn controls. table 16 provides a summary of these control signals and their effect on the pio latches/ffs. note that all control signals are optionally invertible. ta b le 16. pio register control signals ? option description and output ? logical ? and ? of ? signals ? on ? outdd ? and ? clock. nand output ? logical ? nand ? of ? signals ? on ? outdd ? and ? clock. or output ? logical ? or ? of ? signals ? on ? outdd ? and ? clock. nor output ? logical ? nor ? of ? signals ? on ? outdd ? and ? clock. xor output ? logical ? xor ? of ? signals ? on ? outdd ? and ? clock. xnor output ? logical ? xnor ? of ? signals ? on ? outdd ? and ? clock. ? control ? signal effect/functionality edge ? clock ? (eclk) ? clocks ? input ? fast-capture ? latch; ? option- ally ? clocks ? output ? ff, ? or 3-state ? ff, ? or ? pio ? shift ? registers. system ? clock ? (sclk) clocks ? input ? latch/ff; ? optionally ? clocks ? output ? ff, ? or ? 3-state ? ff, ? or ? pio ? shift ? registers. clock ? enable ? (ce) optionally ? enables/disables ? input ? ff ? (not ? available ? for ? input ? latch ? mode); ? optionally ? enables/disables ? output ? ff; ? separate ? ce ? inversion ? capability ? for ? input ? and ? output. local ? set/ reset ? (lsr) option ? to ? disable; ? affects ? input ? latch/ff, ? output ? ff, ? and ? 3-state ? ff ? if ? enabled. global ? set/ reset ? (gsrn) option ? to ? enable ? or ? disable ? per ? pio ? after ? initial ? configuration. set/reset ? mode the ? input ? latch/ff, ? output ? ff, ? and ? 3- state ? ff ? are ? individually ? set ? or ? reset ? by ? both ? the ? lsr ? and ? gsrn ? inputs.
lattice semiconductor 37 data sheet november, 2002 orca series 4 fpgas programmable input/output cells (continued) i/o banks and groups flexible i/o features allow the user to select the type of i/o needed to meet different high-speed interface requirements and these i/os require different input ref- erences or supply voltages. the perimeter of the device is divided into eight banks of pio buffers, as shown in figure 23, and for each bank there is a separate v dd io that supplies the correct input and output voltage for a particular standard. the user must supply the appropri- ate power supply to the v dd io pin. within a bank, sev- eral i/o standards may be mixed as long as they use a common v dd io. the shaded section of the i/o banks in figure 23 (banks 2, 3, and 4) are removed for fpscs, to allow the embedded block to be placed on the side of the fpga array. bank 1 and bank 5 are also e xtended to the corners in fpscs to incorporate more fpga i/os. some interface standards require a speci ed threshold v oltage known as v ref. to accommodate various v ref requirements, each bank is further divided into groups. in these modes, where a particular v ref is required, the device is automatically programmed to dedicate a v ref pin for each group of pios within a bank. the appropriate v ref v oltage must be supplied by the user and connected to the v ref pin for each group. the v ref is dedicated exclusively to the group and cannot be intermixed within the group with other signaling requiring other v ref voltages. however, pins not requiring v ref can be mixed in the same group. when used to supply a reference voltage the v ref pad is no longer available to the user for general use. the v ref inputs should be well isolated to keep the reference v oltage at a consistent level. t able ? 17 . compatible mixed i/o standards ? 0205(f). figure 23 . orca high-speed i/o banks differential i/o (lvds and lvpecl) series 4 devices support differential input, output, and input/output capabilities through pairs of pios. the two standards supported are lvds and lvpecl. the lvds differential pair i/o standard allows for high- speed, low-voltage swing and low-power interfaces de ned by industry standards: ansi/tia/eia-644 and ieee 1596.3 ssi-lvds . the general purpose standard is supplied without the need for an input reference sup- ply and uses a low switching voltage which translates to low ac power dissipation. the orca lvds i/o provides an integrated 100 ? ter- mination resistor used to provide a differential voltage across the inputs of the receiver. the on-chip integra- tion provides termination of the lvds receiver without the need of discrete external board resistors. the user has the programmable option to enable termination per receiver pair for point-to-point applications or in multi- point interfaces limit the use of termination to bussed pairs. if the user chooses to terminate any differential receiver, a single lvds_r pin is dedicated to connect a single 100 ? ( 1%) resistor to v ss which then enables an internal resistor matching circuit to provide a bal- ance 100 ? ( 10%) termination across all process, v oltage, and temperature. experiments have also shown that enabling this 100 ? matching resistor for l vds outputs also improves performance. v dd io ? bank v oltage compatible ? standards 3.3 ? vl vttl, ? sstl3-i, ? sstl3-ii, ? gtl+, ? gtl, ? l vpecl, ? pecl 2.5 ? vl vcmos2, ? sstl2-i, ? sstl2-ii, ? l vds 1.8 ? vl vcmos18 1.5 ? v hstl ? i, ? hstl ? iii, ? hstl ? iv plc array (tc) (tl) (bc) (bl) (cl) bank 0 bank 1 bank 5 bank 6 bank 7 (tr) (br) (cr) bank 2 bank 3 bank 4
38 38 lattice semiconductor data sheet november, 2002 orca series 4 fpgas programmable input/output cells (continued) high-speed memory interfaces pio features allow high-speed interfaces to external sram and/or dram devices. series 4 i/o meet 200 mhz zbt requirements when switching between write and read cycles. zbt allows 100% use of bus cycles during back-to-back read/write and write/read cycles. however this maximum utilization of the bus increases probability of bus contention when the inter- f aced devices attempt to drive the bus to opposite logic v alues. the lvttl i/o interfaces directly with commer- cial zbt srams signalling and allows the versatility to program the fpga drive strengths from 6 ma to 24 ma. ddr allows data to be read on both the rising and the f alling edge of the clock which delivers twice the band- width. ddr doubles the memory speed from sdrams or srams without the need to increase clock fre- quency. the e xibility of the pio allows at least 156 mhz/312 mbits per second performance using the sstl i/o or hstl i/o features of the series 4 devices. high-speed networking interfaces series 4 devices support many i/o standards used in networking. two examples of this are the xgmii stan- dard for 10 gbe (hstl or sstl i/os) and the spi-4 standard for various 10 gbits/s network interfaces (lvds i/os). both operate as a point-to-point link between devices that are forward clocked and transmit data on both clock edges (ddr). the xgmii interface is 36-bits wide per data ow direction and the spi-4 interface is a 16-bit interface. the xgmii speci cation is 156 mhz/312 mbits/s and the spi-4 speci cation that can be met is 325 mhz/650 mbits/s. more information about using orca for these applications can be found in the associated application note. bus hold each pio can be programmed with a keepermode f eature. this element is user programmed for bus hold requirements. this mode retains the last known state of a bus when the bus goes into 3-state. it prevents oat- ing busses and saves system power. pio downlink/uplink (shift registers) each group of four pios in a pic have access to an input/output shift register as shown in figure 24. this f eature allows high-speed input data to be divided down by 1/2 or 1/4 and output data can be multiplied by 2x or 4x its internal speed. both the input and output shift registers can be programmed to operate at the same time and are controlled by the same clock and control signals. f or input shift mode, the data from indd from the pio is connected to the input shift register. the input data is divided down and is driven to the routing through the insh nodes. for output shift mode, the data from the outsh nodes are driven from the internal routing and connects to the output shift register. this output data is m ultiplied up and driven to the outdd signal on the pios. in 2x output mode or input mode, two of the four i/os in a pic can use the shift registers. while in 4x mode, only one i/o can use the shift registers. this also means that all differential i/os on a series 4 device can use 2x shift register mode, but 4x mode is only avail- able for half of the differential i/os. in 4x input mode, all the insh nodes are used, while 2x mode uses insh4 and insh3 for one shift register and insh2 and insh1 for the second shift register. simi- larly, the output shift register in 4x mode uses all the outsh signals. outsh2 and outsh1 are used for 2x output mode for one shift register and outsh4 and outsh3 are used for the other output shift register.
data sheet november, 2002 lattice semiconductor 39 orca series 4 fpgas programmable input/output cells (continued) 0204(f). figure 24. pio shift register indd outsh outdd pio indd outsh outdd pio indd outsh outdd pio indd outsh outdd pio shift register out from fpga shift register into fpga clk outsh1 outsh2 outsh3 outsh4 insh1 intsh2 insh3 insh4 special function blocks special function blocks in the series 4 provide extra capabilities beyond general fpga operation. these b locks reside in the corners and mids (middle inter- quad areas) of the fpga array. internal oscillator the internal oscillator resides in the upper left corner of the fpga array. it has output clock frequencies of 1.25 mhz and 10 mhz. the internal oscillator is the source of the internal cclk used for con guration. it may also be used after con guration as a general- purpose clock signal. global set/reset (gsrn) the gsrn logic resides in the upper-left corner of the fpga. gsrn is an invertible, default, active-low signal that is used to reset all of the user-accessible latches/ ffs on the device. gsrn is automatically asserted at powerup and during con guration of the device. the timing of the release of gsrn at the end of con g- uration can be programmed in the start-up logic described below. following con guration, gsrn may be connected to the reset pin via dedicated routing, or it may be connected to any signal via normal routing. gsrn can also be controlled via a system bus register command. within each pfu and pio, individual ffs and latches can be programmed to either be set or reset when gsrn is asserted. series 4 allows individ- ual pfus and pios to turn off the gsrn signal to its latches/ffs after con guration. the reset input pad has a special relationship to gsrn. during con guration, the reset input pad always initiates a con guration abort, as described in the fpga states of operation section. after con gura- tion, the gsrn can either be disabled (the default), directly connected to the reset input pad, or sourced by a lower-right corner signal. if the reset input pad is not used as a global reset after con guration, this pad can be used as a normal input pad.
40 40 lattice semiconductor data sheet november, 2002 orca series 4 fpgas special function blocks (continued) start-up logic the start-up logic block can be con gured to coordi- nate the relative timing of the release of gsrn, the activation of all user i/os, and the assertion of the done signal at the end of con guration. if a start-up clock is used to time these events, the start-up clock can come from cclk, or it can be routed into the start- up block using upper-left corner routing resources. t emperature sensing the built-in temperature-sensing diodes allow junction temperature to be measured during device operation. a physical pin (ptemp) is dedicated for monitoring device junction temperature. ptemp works by forcing a 10 a current in the forward direction, and then mea- suring the resulting voltage. the voltage decreases with increasing temperature at approximately ?1.69 mv/ ? c. a typical device with a 85 ? c device tem- perature will measure approximately 630 mv. boundary-scan the ieee standards 1149.1 and 1149.2 ( ieee stan- dard test access port and boundary-scan architecture) are implemented in the orca series of fpgas. it allows users to ef ciently test the interconnection between integrated circuits on a pcb as well as test the integrated circuit itself. the ieee 1149 standard is a well-de ned protocol that ensures interoperability among boundary-scan (bscan) equipped devices from different vendors. series 4 fpgas are also compliant to ieee standard 1532/d1. this standard for boundary-scan based in- system con guration of programmable devices pro- vides a standardized programming access and meth- odology for fpgas. a device, or set of devices, implementing this standard may be programmed, read back, erased veri ed, singly or concurrently, with a standard set of resources. the ieee 1149 standards de ne a test access port (tap) that consists of a four-pin interface with an optional reset pin for boundary-scan testing of inte- gr ated circuits in a system. the orca series fpga provides four interface pins: test data in (tdi), test mode select (tms), test clock (tck), and test data out (tdo). the prgm pin used to recon gure the device also resets the boundary-scan logic. the user test host serially loads test commands and test data into the fpga through these pins to drive out- puts and examine inputs. in the con guration shown in figure 26, where boundary-scan is used to test ics, test data is transmitted serially into tdi of the rst bscan device (u1), through tdo/tdi connections between bscan devices (u2 and u3), and out tdo of the last bscan device (u4). in this con guration, the tms and tck signals are routed to all boundary-scan ics in parallel so that all boundary-scan components operate in the same state. in other con gurations, mul- tiple scan paths are used instead of a single ring. when m ultiple scan paths are used, each ring is indepen- dently controlled by its own tms and tck signals. figure 26 provides a system interface for components used in the boundary-scan testing of pcbs. the three major components shown are the test host, boundary- scan support circuit, and the devices under test (duts). the duts shown here are orca series fpgas with dedicated boundary-scan circuitry. the test host is normally one of the following: automatic test equipment (ate), a workstation, a pc, or a micropro- cessor. 5-5972(f) ke y:bsc = boundary-scan cell, bdc = bidirectional data cell, and dcc = data control cell. figure 25. printed-circuit board with boundary-scan circuitry instruction tdo register bypass register tck tms tdi scan out scan in scan out scan in scan in scan out bsc bdc dcc scan out scan in tapc p_in p_in p_out p_in p_ts p_out p_ts p_in p_out p_ts p_out p_ts pl[ij] pt[ij] pr[ij] pb[ij] bdc dcc plc array bdc dcc bdc dcc bsc bsc bsc see enlarged veiw below tms tdi tck tdo tms tdi tck tdo tms tdi tck tdo tms tdi tck tdo u1 u2 u3 u4 tdi tck tdo tms net a net b net c s
data sheet november, 2002 lattice semiconductor 41 orca series 4 fpgas special function blocks (continued) 5-6765(f) figure 26. boundary-scan interface d[7:0] intr micro- processor d[7:0] ce ra r/w dav int sp tms0 tck tdi tdo tdi tms tck tdo orca series fpga tdi orca series fpga tms tck tdo tdi tms tck tdo orca series fpga boundary- scan master (bsm) (dut) (dut) (dut) the boundary-scan support circuit shown in figure 26 is the 497aa boundary-scan master (bsm). the bsm off-loads tasks from the test host to increase test throughput. to interface between the test host and the duts, the bsm has a general mpi and provides paral- lel-to-serial/serial-to-parallel conversion, as well as three 8k data buffers. the bsm also increases test throughput with a dedicated automatic test-pattern generator and with compression of the test response with a signature analysis register. the pc-based boundary-scan test card/software allows a user to quickly prototype a boundary-scan test setup. boundary-scan instructions the series 4 boundary-scan circuitry supports a total of 18 instructions. this includes ten ieee 1149.1 , 1149.2, and 1532/d1 instructions, one optional ieee 1149.3 instruction, two ieee 1532/d1 optional instruc- tions, and ve orca -de ned instructions. there are also 16 other scan chain instructions that are used only during factory device testing and will not be discussed in this data sheet. a 6-bit wide instruction register sup- ports all the instructions listed in table 18. the bypass instruction passes data intentionally from tdi to tdo after being clocked by tck. ta b le 18. boundary-scan instructions code instruction 000000 extest 000001 sample 000011 preload 000100 runbist 000101 idcode 000110 usercode 001000 isc_enable 001001 isc_program 001010 isc_noop 001011 isc_disable 001101 isc_program_usercode 001110 isc_read 010001 plc_scan_ring1 010010 plc_scan_ring2 010011 plc_scan_ring3 010100 ram_write 010101 ram_read 111111 bypass
42 42 lattice semiconductor data sheet november, 2002 orca series 4 fpgas special function blocks (continued) the external test (extest) instruction allows the inter- connections between ics in a system to be tested for opens and stuck-at faults. if an extest instruction is performed for the system shown in figure 25, the con- nections between u1 and u2 (shown by nets a, b, and c) can be tested by driving a value onto the given nets from one device and then determining whether this same value is seen at the other device. this is determined by shifting 3 bits of data for each pin (one f or the output value, one for captured input value, and one for the 3-state value) through a boundary scan reg- ister (bsr) until each one aligns to the appropriate pin. then, based upon the value of the 3-state data bit for each pin, either the i/o pad is driven to the value given in the output register of the bsr, or an input signal is applied at the pin. in either case, the bsr input register is updated with the input value from the i/o pad, which allows it to be shifted out tdo. typically, the user will use the preload instruction to shift in the rst test stimulus for the extest instruction. note that series 4 boundary scan includes the ability to perform a self- monitor on each i/o pin by driving out a value from the output register and checking for this value at the input register of the same i/o pad. the sample instruction is useful for system debug- ging and fault diagnosis by allowing the data at the fpga?s i/os to be observed during normal operation. the data for all of the i/os is captured simultaneously into the bsr, allowing them to be shifted-out tdo to the test host. since each i/o buffer in the pios is bidi- rectional, two pieces of data are captured for each i/o pad: the value at the i/o pad and the value of the 3- state control signal. the preload instruction is used to allow the scan- ning of the boundary-scan register without causing interference to the normal operation of the on-chip sys- tem logic. in turn it allows an initial data pattern to be placed at the latched parallel outputs of bsr prior to selection of another boundary scan test operation. for e xample, prior to selection of the extest instruction, data can be loaded onto the latched parallel outputs using preload. as soon as the extest instruction has been transferred to the parallel output of the instruction register, the preloaded data is driven through the system output pins. this ensures that known data, consistent at the board level, is driven immediately when the extest instruction is entered. without preload, indeterminate data would be driven until the rst scan sequence had been com- pleted. there are six orca -de ned instructions. the plc scan rings 1, 2, and 3 (psr1, psr2, psr3) allow user- de ned internal scan paths using the plc latches/ffs and routing interface. the ram_write enable (ram_w) instruction allows the user to serially con g- ure the fpga through tdi. the ram_read enable (ram_r) allows the user to read back ram contents on tdo after con guration. the idcode instruction allows the user to capture a 32-bit identi cation code that is unique to each device and serially output it at tdo. the idcode format is shown in table 19. an optional ieee 1149.3 instruction runbist has been implemented. this instruction is used to invoke the built in self test (bist) of regular structures like rams, roms, fifos, etc., and the surrounding ran- dom logic in the circuit. the usercode instruction shifts out a 32-bit id seri- ally at tdo. at powerup, a default value of the idcode with the manufacturer eld (11-bits) set to all zeros is loaded. the user can set this 11-bit value to a user- de ned number during device con guration. it may also be changed by the isc_program_usercode instruction, described later. also implemented in series 4 devices is the ieee 1532/d1 standards for in-system con guration for pro- gr ammable logic devices. included are 4 mandatory and 2 optional instructions de ned in the standards. isc_enable, isc_program, isc_noop, and isc_disable are the four mandatory instructions. isc_enable initializes the devices for all subsequent isc instructions. the isc_program instruction is similar to the ram_write instruction implemented in all orca devices where the user must monitor the pinitn pin for a high indicating the end of initialization and a successful con guration can be started. the isc_program instruction is used to program the con guration memory through a dedicated isc_pdata register. the isc_noop instruction is user when pro- gr amming multiple devices in parallel. during this mode tdi and tdo behave like bypass. the data shifted through tdi is shifted out through tdo. however the output pins remain in control of the bsr unlike bypass where they are driven by the system logic. the isc_disable is used upon completion of the isc programming. no new isc instructions will be operable without another isc_enable instruction. optional 1532/d1 instructions include isc_program_usercode. when this instruction is loaded, the user shifts all 32-bits of a user-de ned id (lsb rst) through tdi. this overwrites any id previ- ously loaded into the id register. this id can then be read back through the usercode instruction de ned in ieee 1149.2.
data sheet november, 2002 lattice semiconductor 43 orca series 4 fpgas special function blocks (continued) isc_read is similar to the orca ram_read instruction which allows the user to readback the con guration ram contents serially out on tdo. both must monitor the pdone signal to determine weather or not con guration is completed. isc_read used a 1-bit register to synchronously readback data coming from the con guration mem- ory. the readback data is clocked into the isc_read data register and then clocked out tdo on the falling edge or tck. ta b le 19. series 4e boundary-scan vendor-id codes * plc array size of fpga, reverse bit order. note: table assumes version 0. device version ? (4 ? bit) part * ? (10 ? bit) family ? (6 ? bit) manufacturer ? (11 ? bit) lsb ? (1 ? bit) or4e02 0000 0011100000 001000 00000011101 1 or4e04 0000 0001010000 001000 00000011101 1 or4e06 0000 0000110000 001000 00000011101 1 orca boundary-scan circuitry the orca series boundary-scan circuitry includes a test access port controller (tapc), instruction register (ir), boundary-scan register (bsr), and bypass regis- ter. it also includes circuitry to support the four pre- de ned instructions. figure 27 shows a functional diagram of the boundary- scan circuitry that is implemented in the orca series. the input pins? (tms, tck, and tdi) locations vary depending on the part, and the output pin is the dedi- cated tdo/rd_data output pad. test data in (tdi) is the serial input data. test mode select (tms) controls the boundary-scan test access port controller (tapc). t est clock (tck) is the test clock on the board. the bsr is a series connection of boundary-scan cells (bscs) around the periphery of the ic. each i/o pad on the fpga, except for cclk, done, and the boundary- scan pins (tck, tdi, tms, and tdo), is included in the bsr. the rst bsc in the bsr (connected to tdi) is located in the rst pio i/o pad on the left of the top side of the fpga (pta pio). the bsr proceeds clockwise around the top, right, bottom, and left sides of the array. the last bsc in the bsr (connected to tdo) is located on the top of the left side of the array (pl1d). the bypass instruction uses a single ff, which resyn- chronizes test data that is not part of the current scan operation. in a bypass instruction, test data received on tdi is shifted out of the bypass register to tdo. since the bsr (which requires a two ff delay for each pad) is bypassed, test throughput is increased when devices that are not part of a test operation are bypassed. the boundary-scan logic is enabled before and during con guration. after con guration, a con guration option determines whether or not boundary-scan logic is used. the 32-bit boundary-scan identi cation register con- tains the manufacturer?s id number, unique part num- ber, and version (as described earlier). the identi cation register is the default source for data on tdo after reset if the tap controller selects the shift- data-register (shift-dr) instruction. if boundary scan is not used, tms, tdi, and tck become user i/os, and tdo is 3-stated or used in the readback operation.
44 lattice semiconductor data sheet november, 2002 orca series 4 fpgas special function blocks (continued) 5-5768(f).b figure 27. orca series boundary-scan circuitry functional diagram tap controller tms tck boundary-scan register isc read/write registers bypass and isc_default register data mux instruction decoder instruction register m u x reset clock ir shift-ir update-ir pur tdo select enable reset clock dr shift-dr update-dr tdi data registers psr1,psr2,psr3 registers (plcs) configuration register (ram_r, ram_w) prgm i/o buffers v dd v dd v dd v dd idcode/user code register orca series tap controller (tapc) the orca series tap controller (tapc) is a 1149 compatible test access port controller. the 16 jtag state assignments from the ieee 1149 speci cation are used. the tapc is controlled by tck and tms. the t apc states are used for loading the ir to allow three basic functions in testing: providing test stimuli (update-dr), test execution (run-test/idle), and obtaining test responses (capture-dr). the tapc allows the test host to shift in and out both instructions and test data/results. the inputs and outputs of the t apc are provided in the table below. the outputs are primarily the control signals to the instruction register and the data register. ta b le 20. tap controller input/outputs symbol i/o function tms i test ? mode ? select tck i test ? clock pur i powerup ? reset prgm ? i bscan ? reset treset o test ? logic ? reset select o select ? ir ? (high); ? select-dr ? (low) enable o test ? data ? out ? enable capture-dr o capture/parallel ? load-dr capture-ir o capture/parallel ? load-ir shift-dr o shift ? data ? register shift-ir o shift ? instruction ? register update-dr o update/parallel ? load-dr update-ir o update/parallel ? load-ir
data sheet november, 2002 lattice semiconductor 45 orca series 4 fpgas special function blocks (continued) the tapc generates control signals that allow capture, shift, and update operations on the instruction and data registers. in the capture operation, data is loaded into the register. in the shift operation, the captured data is shifted out while new data is shifted in. in the update operation, either the instruction register is loaded for instruc- tion decode, or the boundary-scan register is updated for control of outputs. the test host generates a test by providing input into the orca series tms input synchronous with tck. this sequences the tapc through states in order to perform the desired function on the instruction register or a data register. figure 28 provides a diagram of the state transitions for the tapc. the next state is determined by the tms input value. 5-5370(f) figure 28. tap controller state transition diagram select- dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 1 0 0 10 run-test/ idle 1 test-logic- reset select- ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 1 0 10 00 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 11 0 boundary-scan cells figure 29 is a diagram of the boundary-scan cell (bsc) in the orca series pios. there are four bscs in each pic: one for each pad, except as noted above. the bscs are connected serially to form the bsr. the bsc controls the functionality of the in, out, and 3-state sig- nals for each i/o pad. the bsc allows the i/o to function in either the normal or test mode. normal mode is de ned as when an out- put buffer receives input from the plc array and pro- vides output at the pad or when an input buffer provides input from the pad to the plc array. in the test mode, the bsc executes a boundary-scan operation, such as shifting in scan data from an upstream bsc in the bsr, providing test stimuli to the pad, capturing test data at the pad, etc. the primary functions of the bsc are shifting scan data serially in the bsr and observing input (p_in), output (p_out), and 3-state (p_ts) signals at the pads. the bsc consists of three circuits: the bidirectional data cell is used to access the input and output data, the capture cell is used to capture the status of the i/o pad, and the direction control cell is used to access the 3- state value. all three cells consist of a ff used to shift scan data which feeds a ff to control the i/o buffer. the capture cell is connected serially to the bidirec- tional data cell, which is connected serially to the direc- tion control cell to form a boundary-scan shift register. the tapc signals (capture, update, shiftn, treset, and tck) and the mode signal control the operation of the bsc. the bidirectional data cell is also controlled by the high out/low in (holi) signal generated by the direction control cell. when holi is low, the bidirec- tional data cell receives input buffer data into the bsc. when holi is high, the bsc is loaded with functional data from the plc.
46 lattice semiconductor data sheet november, 2002 orca series 4 fpgas special function blocks (continued) the mode signal is generated from the decode of the instruction register. when the mode signal is high (extest), the scan data is propagated to the output buffer. when the mode signal is low (bypass or sample), functional data from the fpga?s internal logic is propagated to the output buffer. the boundary-scan description language (bsdl) is provided for each device in the orca series of fpgas on the isplever cd. the bsdl is generated from a device pro le, pinout, and other boundary-scan information. 5-2844(f).a figure 29. boundary-scan cell boundary-scan timing to ensure race-free operation, data changes on speci c clock edges. the tms and tdi inputs are clocked in on the r ising edge of tck, while changes on tdo occur on the falling edge of tck. in the execution of an extest instruction, parallel data is output from the bsr to the fpga pads on the falling edge of tck. the maximum fre- quency allowed for tck is 20 mhz. figure 30 shows timing waveforms for an instruction scan operation. the diagram shows the use of tms to sequence the tapc through states. the test host (or bsm) changes data on the falling edge of tck, and it is clocked into the dut on the rising edge. d q d q d q d q p_out holi bidirectional data cell i/o buffer direction control cell mode update/tck scan out tck shiftn/capture p_ts p_in p ad_in p ad_ts p ad_out 0 1 0 1 0 1 0 1 0 1 d q d q scan in 0 1 capture cell inbs (to fpga array)
data sheet november, 2002 lattice semiconductor 47 orca series 4 fpgas special function blocks (continued) 5-5971(f) figure 30. instruction register scan timing diagram tck tms tdi run-test/idle run-test/idle exit1-ir exit2-ir update-ir select-dr-scan capture-ir select-ir-scan test-logic-reset shift-ir pause-ir shift-ir exit1-ir single function blocks most of the special function blocks perform a speci c dedicated function. these functions are data/con gura- tion readback control, global 3-state control (ts_all), internal oscillator generation, gsrn, and start-up logic. readback logic the readback logic can be enabled via a bit stream option or by instantiation of a library readback compo- nent. readback is used to read back the con guration data and, optionally, the state of the pfu outputs. a read- back operation can be done while the fpga is in nor- mal system operation. the readback operation cannot be daisy-chained. to use readback, the user selects options in the bit stream generator in the isplever development system. ta b le 21 provides readback options selected in the bit stream generator tool. the table provides the number of times that the con guration data can be read back. this is intended primarily to give the user control over the security of the fpga?s con guration program. the user can prohibit readback (0), allow a single readback (1), or allow unrestricted readback (u). ta b le 21. readback options readback can be performed via the series 4 mpi or by using dedicated fpga readback controls. if the mpi is enabled, readback via the dedicated fpga readback logic is disabled. readback using the mpi is discussed in the mpi section. the pins used for dedicated readback are readback data (rd_data), read con guration ( rd_cfg ), and con guration clock (cclk). a readback operation is initiated by a high-to-low transition on rd_cfg . the rd_cfg input must remain low during the readback operation. the readback operation can be restarted at frame 0 by driving the rd_cfg pin high, applying at least two rising edges of cclk, and then driving rd_cfg low again. one bit of data is shifted out on rd_data at the rising edge of cclk. the rst start bit of the readback frame is transmitted out several cycles after the rst rising edge of cclk after rd_cfg is input low (see the readback timing characteristics table in the timing characteristics section). to be certain of the start of the readback frame, the data can be monitored for the 01 frame start bit pair. option function 0 prohibit ? readback 1 allow ? one ? readback ? only u allow ? unrestricted ? number ? of ? readbacks
48 48 lattice semiconductor data sheet november, 2002 orca series 4 fpgas special function blocks (continued) readback can be initiated at an address other than frame 0 via the new mpi control registers (see the mp i section for more information). in all cases, readback is performed at sequential addresses from the start address. it should be noted that the rd_data output pin is also used as the dedicated boundary-scan output pin, tdo. if this pin is being used as tdo, the rd_data output from readback can be routed internally to any other pin desired. the rd_cfg input pin is also used to control the global 3-state (ts_all) function. before and during con guration, the ts_all signal is always driven by the rd_cfg input and readback is disabled. after con- guration, the selection as to whether this input drives the readback or global 3-state function is determined by a set of bit stream options. if used as the rd_cfg input for readback, the internal ts_all input can be routed internally to be driven by any input pin. the readback frame contains the con guration data and the state of the internal logic. during readback, the v alue of all registered pfu and pio outputs can be captured. the following options are allowed when doing a capture of the pfu outputs. do not capture data (the data written to the rams, usually 0, will be read back). capture data upon entering readback. capture data based upon a con gurable signal inter- nal to the fpga. if this signal is tied to logic 0, cap- ture rams are written continuously. capture data on either options two or three above. the readback frame has an identical format to that of the con guration data frame, which is discussed later in the con guration data format section. if lut mem- ory is not used as ram and there is no data capture, the readback data (not just the format) will be identical to the con guration data for the same frame. this eases a bitwise comparison between the con guration and readback data. the con guration header, including the length count eld, is not part of the readback frame. the readback frame contains bits in locations not used in the con guration. these locations need to be masked out when comparing the con guration and readback frames. the development system optionally provides a readback bit stream to compare to readback data from the fpga. also note that if any of the luts are used as ram and new data is written to them, these bits will not have the same values as the original con guration data frame either. global 3-state control (ts_all) to increase the testability of the orca series fpgas, the global 3-state function (ts_all) disables the device. the ts_all signal is driven from either an e xternal pin or an internal signal. before and during con guration, the ts_all signal is driven by the input pad rd_cfg . after con guration, the ts_all signal can be disabled, driven from the rd_cfg input pad, or driven by a general routing signal in the upper right cor- ner. before con guration, ts_all is active-low; after con guration, the sense of ts_all can be inverted. the following occur when ts_all is activated: all of the user i/o output buffers are 3-stated, the user i/o input buffers are pulled up (with the pull- down disabled), and the input buffers are con gured with ttl input thresholds. the tdo/rd_data output buffer is 3-stated. the rd_cfg , reset , and prgm input buffers remain active with a pull-up. the done output buffer is 3-stated, and the input b uffer is pulled up.
lattice semiconductor 49 data sheet november, 2002 orca series 4 fpgas microprocessor interface (mpi) the series 4 fpgas have a dedicated synchronous mpi function block. the mpi is programmable to oper- ate with po w erpc /powerquicc mpc860/mpc8260 series microprocessors. the mpi implements an 8-, 16-, or 32-bit interface with 1-bit, 2-bit, or 4-bit parity to the host processor ( po w erpc ) that can be used for con guration and readback of the fpga as well as for user-de ned data processing and general monitoring of fpga functions. in addition to dedicated-function registers, the mpi bridges to the amba embedded sys- tem bus through which the po w erpc bus master can access the fpga con guration logic, ebr and other user logic. there is also capability to interrupt the host processor either by a hard interrupt or by having the host processor poll the mpi and the embedded system bus. the control portion of the mpi is available following powerup of the fpga if the mode pins specify mpi mode, even if the fpga is not yet con gured. the width of the data port is selectable among 8-, 16-, or 32-bit and the parity bus can be 1-, 2-, or 4-bit. in con- guration mode the data and parity bus width are related to the state of the m[0:3] mode pins. for post- con guration use, the mpi must be included in the con- guration bit stream by using an mpi library element in y our design from the orca macro library, or by setting the bit of the mpi con guration control register prior to the start of con guration. the user can also enable and disable the parity bus through the con guration bit stream. these pads can be used as general i/o when they are not needed for mpi use. ta b le 22 shows the interface signals that are used to interface series 4 devices to a po w erpc mpc860/ mpc8260 device. more information is available in the series 4 mpi and system bus application note. the orca fpga is a memory-mapped peripheral to the po w erpc processor. the mpi interfaces to the user-programmable fpga logic using the amba embedded system bus.the mpi has access to a series of addressable registers made accessible by the amba system bus that provide mpi control and status, con g- uration and readback data transfer, fpga device iden- ti cation, and a dedicated user scratchpad register. all registers are 8 bits wide. the address map for these registers and the user-logic address space utilize the same registers as the amba embedded system bus. embedded system bus (esb) implemented using the open standard, on-chip amba - ahb 2.0 speci cation bus, the series 4 devices con- nects all the fpga elements together with a standard- ized bus framework. the esb facilitates communication among mpi, con guration, ebrs, and user logic in all the generic fpga devices. ahb serves the need for high-performance system-on-chip ? (soc) as well as aligning with current synthesis design ow s. multiple bus masters optimizes system perfor- mance by sharing resources between different bus masters such as the mpi and con guration logic. the wide data bus con guration of 32-bits with 4-bit parity supports the high-bandwidth of data-intensive applica- tions of using the wide on-chip memory. amba enhances a reusable design methodology by de ning a common backbone for ip modules. the esb is a synchronous bus that is driven by either the mpi clock, internal oscillator, cclk (slave con gu- r ation modes), tck (jtag con guration modes), or by a user clock from routing. in fpscs, a clock from the embedded block can also drive the mpi clock. during initial con guration and recon guration the bus clock is defaulted to the con guration clock. the post con gu- r ation clock source is set during con guration. the user has the ability to program several slaves through the user logic interface. embedded block ram also inter- f aces seamlessly to the system bus. a single bus arbiter controls the traf c on the bus by ensuring only one master has access to the bus at any time. the arbiter monitors a number of different requests to use the bus and decides which request is currently the highest priority. the con guration modes have the highest priority and overrides all normal user modes. priority can be programmed between mpi and user logic at con guration in generic fpgas. if no pri- ority is set a round-robin approach is used by granting the next requesting master in a rotating x ed order. several interfaces exist between the esb and other fpga elements. the mpi interface acts as a bridge between the external microprocessor bus and esb. the mpi may work in an independent clock domain from the esb if the esb clock is not sourced from the e xternal microprocessor clock. pipelined operation allows high-speed memory interface to the ebr and peripheral access without the requirement for addi- tional cycles on the bus. burst transfers allow optimal use of the memory interface by giving advance infor- mation of the nature of the transfers. ta b le 23 is a listing of the esb register le and brief descriptions. table 24 shows the system interrupt reg- isters and table 25 and table 26 show the fpga status and command registers, all with brief descriptions. more information is available in the series 4 mpi and system bus application note.
50 lattice semiconductor data sheet november, 2002 orca series 4 fpgas microprocessor interface (continued) ta b le 22. mpc 860 to orca mpi interconnection po werpc signal orca pin name mpi i/o function d[0: n ] d[0: n ] i/o 8, 16, 32-bit data bus. dp[0: m ] dp[0: m ] i/o selectable parity bus width from1, 2, and 4-bit. a[14:31] ppc_a[14:31] i 32-bit mpi address bus. ts mpi_strb it r ansfer start signal. b urst mpi_b urst i active-low indicates burst transfer in-progress. high indicates current transfer not a burst. ? cs0 i active-low mpi select. ? cs1 i active-high mpi select. clkout mpi_clk i po w erpc interface clock. rd/wr mpi_rw i read (high)/write (low) signal. t a mpi_a ck o active-low transfer acknowledge signal. bdip mpi_bdip i active-low burst transfer in progress signal indicates that the second beat in front of the current one is requested by the master. negated before the burst transfer ends to abort the burst data phase. any of irq [7:0] mpi_irq o active-low interrupt request signal. tea mpi_tea o active-low indicates mpi detects a bus error on the internal system bus for current transaction. retr y mpi_r tr y o requests the mpc860/mpc8260 to relinquish the bus and retry the cycle. tsz[0:1] mpi_tsz[0:1] i driven to indicate the data transfer size for the transaction (byte, half-word, w ord).
lattice semiconductor 51 data sheet november, 2002 orca series 4 fpgas microprocessor interface (continued) ta b le 23. embedded system bus/mpi registers note: ro = read only, r/w = read/write ta b le 24. interrupt register space assignments note: ro = read only, r/w = read/write. f or internal system bus, bit 7 is most signi cant bit, for mpi bit 0 is most signi cant bit. register byte read/write initial value description 00 03-00 ro ? 32-bit device id 01 07-04 r/w ? scratchpad register 02 0b-08 r/w ? command register 03 0f-0c ro ? status register 04 13 r/w ? interrupt enable register ? mpi 12 r/w ? interrupt enable register ? user 11 r/w ? interrupt enable register ? fpsc (unused for fpgas) 10 ro ? interrupt cause register 05 17-14 r/w ? readback address register (14 bits) 06 1b-18 ro ? readback data register 07 1f-1c r/w ? con guration data register 08 23-20 ro ? trap address register 09 27-24 ro ? bus error address register 0a 2b-28 ro ? interrupt vector 1 prede ned by con guration bit stream 0b 2f-2c ro ? interrupt vector 2 prede ned by con guration bit stream 0c 33-30 ro ? interrupt vector 3 prede ned by con guration bit stream 0d 37-34 ro ? interrupt vector 4 prede ned by con guration bit stream 0e 3b-38 ro ? interrupt vector 5 prede ned by con guration bit stream 0f 3f-3c ro ? interrupt vector 6 prede ned by con guration bit stream 10 43?40 ? ? top-left ppll 11 47?44 ? ? top-left hpll 14 53?50 ? ? top-right ppll 18 63?60 ? ? bottom-left ppll 19 67?64 ? ? bottom-left hpll 1c 73?70 ? ? bottom-right ppll byte bit read/write description 13 7-0 r/w interrupt enable register ? mpi 12 7-0 r/w interrupt enable register ? user 11 7-0 r/w interrupt enable register ? fpsc 10 interrupt cause registers 7r o user_irq_general; 6r o user_irq_slave; 5r o user_irq_master; 4r o cfg_irq_data; 3r o err_flag 1 2r o mpi_irq 1r o fpsc_irq_slave; 0r o fpsc_irq_master
52 lattice semiconductor data sheet november, 2002 orca series 4 fpgas microprocessor interface (continued) ta b le 25. status register space assignments notes: ro = read only. for internal system bus, bit 7 is most signi cant bit, for mpi bit 0 is most signi cant bit. ta b le 26. command register space assignments note: r/w = read/write. for internal system bus; bit 7 is most signi cant bit, for mpi bit 0 is most signi cant bit. byte bit read/write description 0f 7:0 ? reserved 0e 7:0 ? reserved od 7 ro con guration write data acknowledge 6r o readback data ready 5r o unassigned (zero) 4r o unassigned (zero) 3r o fpsc_bit_err 2r o ram_bit_err 1ro con guration write data size (1, 2, or 4 bytes) 0r o use with above for hsize[1:0] (byte, half-word, word) 0c 7 ro readback addresses out of range 6r o error response received by cfg from system bus 5r o error responses received by cfg from system bus 4r o cfg_data_lost 3r o done 2r o init_n 1r o err_flag 1 0r o err_flag 0 byte bit read/write description 0b 7:0 ? reserved 0a 7:0 ? reserved 09 7 r/w sys_gsr (gsr input) 6 r/w sys_rd_cfg (similar to fpga pin rd_cfgn, but active high) 5 r/w prgm from mpi > (similar to fpga pin, but active high) 4 r/w prgm from user > (similar to fpga pin, but active high) 3 r/w prgm from fpsc > (similar to fpga pin, but active high) 2 r/w lock from mpi 1 r/w lock from user 0 r/w lock from fpsc 08 7 r/w bus reset from mpi (resets system bus and registers) 6 r/w bus reset from user (resets system bus and registers) 5 r/w bus reset from fpsc (resets system bus and registers) 4 r/w sys_daisy 3 r/w repeat_rdbk (don't increment readback address) 2 r/w mpi_usr_enable 1 r/w readback data size (1, 2, or 4 bytes) 0 r/w use with above for hsize[1:0]
lattice semiconductor 53 data sheet november, 2002 orca series 4 fpgas phase-locked loops (plls) there are eight plls available to perform many clock modi cation and clock conditioning functions on the series 4 fpgas. six of the plls are programmable allowing the user the e xibility to con gure the pll to manipulate the frequency, phase, and duty cycle of a clock signal. four of the programmable plls (pplls) are capable of manipu- lating and conditioning clocks from 15 mhz to 200 mhz and two others (hpplls) are capable of manipulating and conditioning clocks from 60 mhz to 420 mhz. frequencies can be adjusted from 1/64x to 64x the input clock fre- quency. each programmable pll provides two outputs that have different multiplication factors with the same phase relationships. duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. an automatic delay compensation mode is available for phase delay. each ppll and hppll provides two outputs that can have programmable (45 degree increments) phase differences. the pplls and hpplls can be utilized to eliminate skew between the clock input pad and the internal clock inputs across the entire device. both the pplls or the hpplls can drive onto the primary and secondary clock networks inside the fpga. each can take a clock input from the dedicated pad or differential pair of pads in its corner or from general routing resources. functionality of the pplls and hpplls is programmed during operation through a control register internal to the fpga array or via the con guration bit stream. the embedded system bus enables access to these registers (see ta b le 23). there is also a pll output signal, lock, that indicates a stable output clock state. ta b le 27. ppll speci cations additional highly tuned and characterized dedicated phase-locked loops (dplls) are included to ease system designs. these dplls meet itu-t g.811 primary clocking speci cations and enable system designers to target ve ry tightly speci ed clock conditioning not available in the programmable pplls. they also provide enhanced jitter ltering to reduce the amount of input jitter that is transferred to the pll output when used in any application. dplls are targeted to low-speed ds1 and e1 networking systems (pll1) and high-speed sonet/sdh network- ing sts-3 and stm-1 networking systems (pll2). p arameter min nom max unit v dd 15 1.425 1.5 1.575 v v dd 33 3.0 3.3 3.6 v operating temp ?40 ? 125 c input clock frequency (no division) ppll 2.0 ? 200 mhz hppll 7.5 ? 420 output clock frequency ppll 15 ? 200 mhz hppll 60 ? 420 input duty cycle 30 ? 70 % output duty cycle 45 50 55 % lock time ? <50 ? s f requency multiplication up to 64x ? f requency division down to 1/64x ? duty cycle adjust of output clock 12.5, 25, 37.5, 50, 62.5, 75, 87.5 % delay adjust of output clock 0, 45, 90, 135, 180, 225, 270, 315 degrees phase shift between mclk and nclk 0, 45, 90, 135, 180, 225, 270, 315 degrees
54 lattice semiconductor data sheet november, 2002 orca series 4 fpgas phase-locked loops (continued) tab le 28 . ds-1/e-1 pll1 speci cations a dedicated pin pll_vf is needed for externally connecting a low pass lter circuit. this provides the speci ed ds?1/e?1 pll operating condition. 0203(f). figure 31. pll_vf external requirements p arameter min nom max unit v dd 15 1.425 1.5 1.575 v v dd 33 3.0 3.3 3.6 v operating temp ?40 ? 125 c input clock frequency 1.0 ? 2.5 mhz output clock frequency 1.0 ? 2.5 mhz input duty cycle 30 ? 70 % output duty cycle 47 50 53 % lock time ? <1200 ? s pll_vf c 1 c 2 r 1 r 1 = 6 k ? 1% c 1 = 100 pf 5% c 2 = 0.01 f 5% v ss
lattice semiconductor 55 data sheet november, 2002 orca series 4 fpgas phase-locked loops (continued) ta b le 29. sts-3/stm-1 pll2 speci cations all series 4 plls operate from the v dd 33 power supply. care needs to be taken during board layout to properly iso- late and lter this power supply. more information about the plls is available in the series 4 fpga pll elements application note. the location of all eight plls on series 4 fpgas is shown in figure 32 and table 30. 0045(f) figure 32. pll naming scheme ta b le 30. phase-lock loops index p arameter min nom max unit v dd 15 1.425 1.5 1.575 v v dd 33 3.0 3.3 3.6 v operating temp ?40 ? 125 c input clock frequency 140 155.52 170 mhz output clock frequency 140 155.52 170 mhz input duty cycle tolerance 30 ? 70 % output duty cycle 47 50 53 % lock time ? <50 ? s name description [ul][ll][ur][lr]ppll universal user programmable pll (15?200 mhz) [ul][ll]hppll universal user programmable pll (60?420 mhz) urpll1 ds-1/e-1 dedicated pll lrpll2 sts-1/stm-1 dedicated pll lrppll lrpll2 llppll llhppll urppll urpll1 ulppll ulhppll
56 56 lattice semiconductor data sheet november, 2002 orca series 4 fpgas fpga states of operation prior to becoming operational, the fpga goes through a sequence of states, including initialization, con gura- tion, and start-up. figure 33 outlines these three states. 5-4529(f). figure 33. fpga states of operation initialization upon powerup, the device goes through an initialization process. first, an internal power-on-reset circuit is trig- gered when power is applied. when v dd 15 and v dd 33 reach the voltage at which portions of the fpga begin to operate, the i/os are con gured based on the con g- uration mode, as determined by the mode select inputs m[3:0]. a time-out delay is then initiated to allow the power supply voltage to stabilize. the init and done outputs are low. at the end of initialization, the default con guration option is that the con guration ram is written to a low state. this prevents internal shorts prior to con gura- tion. as a con guration option, after the rst con gura- tion (i.e., at recon guration), the user can recon gure without clearing the internal con guration ram rst. the active-low, open-drain initialization signal init is released and must be pulled high by an external resis- tor when initialization is complete. to synchronize the con guration of multiple fpgas, one or more init pins should be wire-anded. if init is held low by one or more fpgas or an external device, the fpga remains in the initialization state. init can be used to signal that the fpgas are not yet initialized. after init goes high f or two internal clock cycles, the mode lines (m[3:0]) are sampled, and the fpga enters the con guration state. the high during con guration (hdc), low during con g- uration ( ldc ), and done signals are active outputs in the fpga?s initialization and con guration states. hdc, ldc , and done can be used to provide control of e xternal logic signals such as reset, bus enable, or prom enable during con guration. for parallel master con guration modes, these signals provide prom enable control and allow the data pins to be shared with user logic signals. if con guration has begun, an assertion of reset or prgm initiates an abort, returning the fpga to the ini- tialization state. the prgm and reset pins must be pulled back high before the fpga will enter the con g- uration state. during the start-up and operating states, only the assertion of prgm causes a recon guration. in the master con guration modes, the fpga is the source of con guration clock (cclk). in this mode, the initialization state is extended to ensure that, in daisy- chain operation, all daisy-chained slave devices are ready. independent of differences in clock rates, master mode devices remain in the initialization state an addi- tional six internal clock cycles after init goes high. when con guration is initiated, a counter in the fpga is set to 0 and begins to count con guration clock cycles applied to the fpga. as each con guration data frame is supplied to the fpga, it is internally assem- b led into data words. each data word is loaded into the internal con guration memory. the con guration load- ing process is complete when the internal length count equals the loaded length count in the length count eld, and the required end of con guration frame is written. during con guration, the pio and plc latches/ffs are held set/reset and the internal slic buffers are 3-stated. the combinatorial logic begins to function as the fpga is con gured. figure 34 shows the general wa ve fo rm of the initialization, con guration, and start- up states. ? active i/o ? release internal reset ? done goes high start-up initialization configuration reset or prgm low prgm low ? clear configuration memory ? init low, hdc high, ldc low operation powerup ? power-on time delay ? m[3:0] mode is selected ? configuration data frame written ? init high, hdc high, ldc low ? dout active yes no no reset , init , or prgm low bit error yes
lattice semiconductor 57 data sheet november, 2002 orca series 4 fpgas fpga states of operation (continued) po wer supply sequencing fpgas are cmos static ram (sram) based program- mable logic devices. the circuitry that the user designs f or the fpga is implemented within the fpga by set- ting multiple sram con guration memory cells. this unique structure as compared with typical cmos cir- cuits lends to having certain powerup voltage and cur- rent requirements. this section describes these related power issues for the orca series 4 fpgas and fpscs. the e xibility of series 4 fpgas lends itself to more power up considerations as it mixes many power sup- plies to meet today?s versatile system standards. the board designer must account for the relationship of the supplies early in board development. the proper sequence of supplies insures that the board will not be troubled with power up issues. the series 4 devices have many new design improve- ments to prevent short-circuit contention. this conten- tion is typically caused by con guration ram cells in the device not all powering up to a q = 0 ram state. in order for this to occur, a minimum current was needed to push the internal circuitry beyond the initial short-cir- cuit-like condition to become a full cmos circuit. series 4 has overcome this requirement through many improvements which have dramatically decreased the adverse effects of internal power up memory conten- tion. at power up, the internal v dd r amp and the duration of the ramp will depend on the amount of dynamic current av ailable from the power supply. if a large amount of current is available, the voltage ramp seen by the device will be very fast. when nal voltage has been reached, this high quiescent current is no longer required. if the available current is limited, the time for the device power to rise will be longer. the voltage r amp should be monotonic with very little or no atten- ing as the supply ramps up. it is also recommended that the supply should not rise and fall as it is powering up as this will cause improper power up behavior. in series 4 devices, it is recommended that the v dd 15 supply pass through its operational threshold voltage of approximately 1 v before the v dd 33 supply reaches its operational threshold of 2.3 v. the current required by both v dd 15 and v dd 33 supplies while it passes through their operational thresholds is approximately between 1 and 2 amperes each. the powering of the v dd io supplies should be after the v dd 15 and v dd 33 supplies reach operational levels. this sequence and supply currents can guarantee that the device will prop- erly power up without any adverse effects. in cases where the power up ramps are greater than 50 ms, it is recommended that prg m pin be held low dur- ing power up. however, this work around is only valid if the power supplies meet the above mentioned current and voltage requirements. the assertion of the prgm will hold off the device from con guration while the device stabilizes and will not counter act any internal power up requirements. con guration the orca series fpga functionality is determined by the state of internal con guration ram. this con gura- tion ram can be loaded in a number of different modes. in these con guration modes, the fpga can act as a master or a slave of other devices in the sys- tem. the decision as to which con guration mode to use is a system design issue. con guration is dis- cussed in detail, including the con guration data format and the con guration modes used to load the con gu- r ation data in the fpga, following a description of the start-up state. start-up after con guration, the fpga enters the start-up phase. this phase is the transition between the con g- uration and operational states and begins when the n umber of cclks received after init goes high is equal to the value of the length count eld in the con g- uration frame and when the end of con guration frame has been written. the system design issue in the start- up phase is to ensure the user i/os become active without inadvertently activating devices in the system or causing bus contention. a second system design concern is the timing of the release of global set/reset of the plc latches/ffs.
58 lattice semiconductor data sheet november, 2002 orca series 4 fpgas fpga states of operation (continued) 5-4482(f) figure 34. initialization/con guration/start-up waveforms initialization configuration start-up operation v dd 15, v dd 33 reset prgm init m[3:0] cclk hdc ldc done user i/o internal reset (gsm)
lattice semiconductor 59 data sheet november, 2002 orca series 4 fpgas fpga states of operation (continued) there are con guration options that control the relative timing of three events: done going high, release of the set/reset of internal ffs, and user i/os becoming active. figure 35 shows the start-up timing for orca fpgas. the system designer determines the relative timing of the i/os becoming active, done going high, and the release of the set/reset of internal ffs. in the orca series fpga, the three events can occur in any arbitrary sequence. this means that they can occur before or after each other, or they can occur simulta- neously. there are four main start-up modes: cclk_nosync, cclk_sync, uclk_nosync, and uclk_sync. the only difference between the modes starting with cclk and those starting with uclk is that for the uclk modes, a user clock must be supplied to the start-up logic. the timing of start-up events is then based upon this user clock, rather than cclk. the dif- f erence between the sync and nosync modes is that for sync mode, the timing of two of the start-up ev ents, release of the set/reset of internal ffs, and the i/os becoming active is triggered by the rise of the e xternal done pin followed by a variable number of r ising clock edges (either cclk or uclk). for the nosync mode, the timing of these two events is based only on either cclk or uclk. done is an open-drain bidirectional pin that may include an optional (enabled by default) pull-up resistor to accommodate wired anding. the open-drain done signals from multiple fpgas can be tied together (anded) with a pull-up (internal or external) and used as an active-high ready signal, an active-low prom enable, or a reset to other portions of the system. when used in sync mode, these anded done pins can be used to synchronize the other two start-up ev ents, since they can all be synchronized to the same e xternal signal. this signal will not rise until all fpgas release their done pins, allowing the signal to be pulled high. an example of using the synchronized modes are the cclk_sync synchronized start-up mode where done is released on the rst cclk rising edge, c1 (see figure 35). since this is a synchronized start-up mode, the open- drain done signal can be held low externally to stop the occurrence of the other two start-up events. once the done pin has been released and pulled up to a high level, the other two start-up events can be pro- gr ammed individually to either happen immediately or after up to four rising edges of cclk (di, di + 1, di + 2, di + 3, di + 4). the default is for both events to happen immediately after done is released and pulled high. a commonly used design technique is to release done one or more clock cycles before allowing the i/o to become active. this allows other con guration devices, such as proms, to be disconnected using the done signal so that there is no bus contention when the i/os become active. in addition to controlling the fpga during start-up, other start-up techniques that av oid contention include using isolation devices between the fpga and other circuits in the system, reassigning i/o locations, and maintaining i/os as 3-stated outputs until contentions are resolved. each of these start-up options can be selected during bit stream generation in isplever, using advanced options. for more information, please see the isplever documentation.
60 lattice semiconductor data sheet november, 2002 orca series 4 fpgas fpga states of operation (continued) 5-2761(f) figure 35. start-up waveforms di c1 c2 c3 c4 f c1 c2 c3 c4 c1 c2 c3 c4 c1, c2, c3, or c4 di + 1 di di + 2 di + 3 di + 4 di + 1 di di + 2 di + 3 di + 4 orca cclk_sync done in u1 u2 u3 u4 f u1 u2 u3 u4 u1 u2 u3 u4 orca uclk_nosync di di + 1 di + 2 di + 3 orca uclk_sync uclk period synchronization uncertainty done in f c1 c1 u1, u2, u3, or u4 done i/o gsrn a ctive done i/o gsrn a ctive done i/o gsrn a ctive done i/o gsrn a ctive uclk f = finished, no more clks required. cclk f orca cclk_nosync di + 4 di + 3 di + 2 di + 1 period
lattice semiconductor 61 data sheet november, 2002 orca series 4 fpgas fpga states of operation (continued) recon guration to recon gure the fpga when the device is operating in the system, a low pulse is input into prgm or one of the program bits in the embedded system bus control register must be set. the con guration data in the fpga is cleared, and the i/os not used for con gura- tion are 3-stated with a pullup. the fpga then samples the mode select inputs and begins recon guration. when recon guration is complete, done is released, allowing it to be pulled high. pa r tial recon guration all orca device families have been designed to allow a partial recon guration of the fpga at any time. this is done by setting a bit stream option in the previous con guration sequence that tells the fpga to not reset all of the con guration ram during a recon guration. then only the con guration frames that are to be modi- ed need to be rewritten, thereby reducing the con gu- r ation time. other bit stream options are also available that allow one portion of the fpga to remain in operation while a partial recon guration is being done. if this is done, the user must be careful to not cause contention between the two con gurations (the bit stream resident in the fpga and the partial recon guration bit stream) as the second recon guration bit stream is being loaded. during a partial re-con guration where the con gura- tion option is set to have the internal logic remain active during con guration the internal sljc bidi signals will always be 3-stated. previous families of orca fpgas w ould allow the bidis to continue to be under user logic control during a partial re-con guration. other con guration options there are many other con guration options available to the user that can be set during bit stream generation in isplever. these include options to enable boundary- scan and/or the mpi and/or the programmable pll b locks, readback options, and options to control and use the internal oscillator after con guration. other useful options that affect the next con guration (not the current con guration process) include options to disable the global set/reset during con guration, dis- able the 3-state of i/os during con guration, and dis- able the reset of internal rams during con guration to allow for partial con gurations (see above). for more information on how to set these and other con guration options, please see the isplever documentation. con guration data format the isplever development system interfaces with front-end design entry tools and provides tools to pro- duce a fully con gured fpga. this section discusses using the isplever development system to generate con guration ram data and then provides the details of the con guration frame format. using isplever to generate con guration ram data the con guration data bit stream de nes the i/o func- tionality, logic, and interconnections within the fpga. the bit stream is generated by the development sys- tem. the bit stream created by the bit stream genera- tion tool is a series of 1s and 0s used to write the fpga con guration ram. it can be loaded into the fpga using one of the con guration modes discussed later. in bit stream generator, the designer selects options that affect the fpga?s functionality. using the output of the bit stream generator, circuit_name.bit , the devel- opment system?s download tool can load the con gura- tion data into the orca series fpga evaluation board from a pc or workstation. a download cable that can be used to download from any pc or workstation supported by isplever is avail- able. this cable allows download to an fpga that can be programmed via the serial con guration interface (requiring the mode pins to be set) or the jtag bound- ary scan interface (not requiring the setting of mode pins). the lead device can then program other fpgas or fpscs on the board via daisy-chaining. alternatively, a user can program a prom (such as a serial rom or a standard eprom) and load the fpga from the prom. the development system?s prom programming tool produces a le in .mcs, .tek or .exo fo r mat.
62 lattice semiconductor data sheet november, 2002 orca series 4 fpgas con guration data format (continued) con guration data frame con guration data can be presented to the fpga in two frame formats: autoincrement and explicit. a detailed description of the frame formats is shown in figure 36, figure 37, and tables table 31 and table 31a. the two modes are similar except that autoincrement mode uses assumed address incrementation to reduce the bit stream size, and explicit mode uses an optional address frame. in both cases, the header frame begins with a series of 1s and a preamble of 0010, followed by a 24-bit length count eld representing the total number of con guration clocks needed to complete the loading of the fpgas. if only series 4 devices are used, a second preamble value of 0100 is supported. if this preamble is found, the series 4 device will expect an expanded length count eld of 32- bits. this allows more larger series 4 fpgas to be con gured through daisy-chaining. f ollowing the header frame is a mandatory id frame. the id frame contains data used to determine if the bit stream is being loaded to the correct type of orca fpga (i.e., a bit stream generated for an or4e06 is being sent to an or4e06). error checking is always enabled for series 4 devices through the use of an 8-bit checksum. fol- lowing the id frame is a 16-bit header to select the portion of the device to be con gured with the following data. the options are an fpga header (shown in table 32), an embedded ram header (shown in table 32a), and an fpsc embedded block header (not shown). a con guration data frame follows the header frame. a data frame starts with a 01-start bit pair and ends with enough 1-stop bit to reach a byte boundary. if subsequent data frames follow the frame address is auto-incre- mented. if using explicit mode, an address frame can follow a data frame, telling the fpga at what address to update the auto-increment counter to for the next data frame. address frame starts with 00. f ollowing all data and address frames is the postamble. the format of the postamble is the same as an address frame with the highest possible address value with the checksum set to all ones, if no other sections of con gura- tion data follow. if another section is to follow, the header starts with 10. 5-5759(f) figure 36. serial con guration data format?autoincrement mode 5-5760(f).a figure 37. serial con guration data format?explicit mode configuration data configuration data 10 01 01 preamble length id frame configuration configuration postamble configuration header 00 00 count data frame 1 data frame 2 preamble length id frame configuration configuration postamble configuration header address 00 count data frame 1 data frame 2 frame 1 configuration data configuration data 10 01 01 00 00
lattice semiconductor 63 data sheet november, 2002 orca series 4 fpgas con guration data format (continued) tab le 31. con guration frame format and contents ta b le 31a. con guration frame format and contents for embedded block ram frame contents description header 11110010 preamble for generic fpga. 24-bit length count con guration bitstream length. 11111111 8-bit trailing header. id frame 0101 1111 1111 1111 id frame header. 44 reserved bits reserved bits set to 0. pa rt id 20-bit part id. checksum 8-bit checksum. 11111111 8 stop bits (high) to separate frames. fpga header 1111 0010 this is a new mandatory header for generic portion. 11111111 8 stop bits (high) to separate frames. fpga address frame 00 address frame header. 14-bit address 14-bit address of generic fpga. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. fpga data frame 01 data frame header. same as generic. alignment bits string of 0 bits added to frame to reach a byte bound- ary. data bits number of data bits depends upon device. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. p ostamble for generic fpga 00 or 10 postamble header, 00 = nish, 10 = more bits coming. 11111111 111111 dummy address. 11111111 11111111 16 stop bits (high). frame contents description ram header 11110001 a mandatory header for ram bitstream portion. 11111111 8 stop bits (high) to separate frames. ram address frame 00 address frame header. same as generic. 6-bit address 6-bit address of ram blocks. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. ram data frame 01 data frame header. same as generic. 000000 six of 0 bits added to reach a byte boundary. 512x18 data bits exact number of bits in a ram block. checksum 8-bit checksum. 11111111 eight stop bits (high) to separate frames. p ostamble for ram 00 or 10 postamble header. 00 = nish, 10 = more bits coming. 111111 dummy address. 11111111 11111111 16 stop bits (high).
64 lattice semiconductor data sheet november, 2002 orca series 4 fpgas con guration data format (continued) the number of frames, number of bits/frame, total number of bits and the required prom size for each series 4 device is shown in table 32 tab le 32. con guration frame size bit stream error checking there are three different types of bit stream error checking performed in the orca series 4 fpgas: id frame, frame alignment, and crc checking. the id data frame is sent to a dedicated location in the fpga. this id frame contains a unique code for the device f or which it was generated. this device code is compared to the internal code of the fpga. any differences are agged as an id error. this frame is automatically created by the bit stream generation program in isplever. each data and address frame in the fpga begins with a frame start pair of bits and ends with eight stop bits set to 1. if any of the previous stop bits were a 0 when a frame start pair is encountered, it is agged as a frame alignment error. error checking is also done on the fpga for each frame by means of a checksum byte. if an error is found on eval- uation of the checksum byte, then a checksum/parity error is agged. the checksum is the xor of all the data b ytes, from the start of frame up to and including the bytes before the checksum. it applies to the id, address, and data frames. when any of the three possible errors occur, the fpga is forced into an idle state, forcing init low. the fpga will remain in this state until either the reset or prgm pins are asserted the pgrm bits of the mpi control register can also be used to reset out of the error condition and restart con guration. if using any of the mpi modes to con gure the fpga, the speci c type of bit stream error is written to one of the mpi registers by the fpga con guration logic. this same information can also be read from the data register when in asynchronous peripheral mode. fpga con guration modes there are twelve methods for con guring the fpga as show in table 33. eleven of the con guration modes are selected on the m0, m1, m2, and m3 inputs. the twelfth con guration mode is accessed through the boundary- scan interface. some modes are used to select the frequency of the internal oscillator, which is the source for cclk in some con guration modes. the nominal frequencies of the internal oscillator are 1.25 mhz and 10 mhz. there are three basic fpga con guration modes: master, slave, and peripheral which includes mpi mode. the con guration data can be transmitted to the fpga serially or in parallel bytes. as a master, the fpga provides the control signals out to strobe data in. as a slave device, a clock is generated externally and provided into the cclk input. in the ve peripheral modes, the fpga acts as a microprocessor peripheral. table 33 lists the functions of the con guration mode pins. devices or4e02 or4e04 or4e06 number of frames 1796 2436 3076 data bits/frame 900 1284 1540 maximum con guration data (number of bits/frame x number of frames) 1,616,400 3,127,824 4,737,040 maximum prom size (bits) (add con guration header and postamble) 1,616,648 3,128,072 4,737,288
lattice semiconductor 65 data sheet november, 2002 orca series 4 fpgas fpga con guration modes (continued) tab le 33. con guration modes master parallel mode the master parallel con guration mode is generally used to interface to industry-standard, byte-wide memory. fig- ure 38 provides the connections for master parallel mode. the fpga outputs an 22-bit address on a[21:0] to mem- ory and reads 1 byte of con guration data on the rising edge of rclk. the parallel bytes are internally serialized starting with the least signi cant bit, d0. d[7:0] of the fpga can be connected to d[7:0] of the microprocessor only if a standard prom le format is used. if a .bit or .rbt le is used from isplever, then the user must mirror the bytes in the .bit or .rbt le or leave the .bit or .rbt le unchanged and connect d[7:0] of the fpga to d[0:7] of the micro- processor. note: m3 = gnd for high-speed cclk; m3 = v dd for low-frequency cclk. 5-9738(f).a figure 38. master parallel con guration schematic in master parallel mode, the starting memory address is 00000 hex, and the fpga increments the address for each b yte loaded. m3 m2 m1 m0 cclk con guration mode data 00 00 output. high-frequency. master serial serial 01 00 output. high-frequency. master parallel 8-bit 01 01 output. high-frequency. asynchronous peripheral 8-bit 01 11 na reserved na 10 00 output. low-frequency. master serial serial 10 01 input. slave parallel 8-bit 10 10 output. mpc860 mpi 8-bit 10 11 output. mpc860 mpi 16-bit 11 00 output. low-frequency. master parallel 8-bit 11 01 output. low-frequency. asynchronous peripheral 8-bit 11 10 output. mpc860 mpi 32-bit 11 11 input. slave serial serial a[21:0] d[7:0] eprom oe ce prgm a[21:0] d[7:0] done orca series fpga dout cclk hdc ldc rclk m2 m1 m0 program v dd to daisy- chained devices
66 66 lattice semiconductor data sheet november, 2002 orca series 4 fpgas fpga con guration modes (continued) one master mode fpga can interface to the memory and provide con guration data on dout to additional fpgas in a daisy-chain. the con guration data on dout is provided synchronously with the rising edge of cclk. the frequency of the cclk output is eight times that of rclk. master serial mode in the master serial mode, the fpga loads the con gu- r ation data from an external serial rom. the con gura- tion data is either loaded automatically at start-up or on a prgm command to recon gure. serial proms can be used to con gure the fpga in the master serial mode. con guration in the master serial mode can be done at powerup and/or upon a con gure command. the sys- tem or the fpga must activate the serial rom's reset /oe and ce inputs. at powerup, the fpga and serial rom each contain internal power-on reset cir- cuitry that allows the fpga to be con gured without the system providing an external signal. the power-on reset circuitry causes the serial rom's internal address pointer to be reset. after powerup, the fpga automati- cally enters its initialization phase. the serial rom/fpga interface used depends on such f actors as the availability of a system reset pulse, avail- ability of an intelligent host to generate a con gure command, whether a single serial rom is used or mul- tiple serial roms are cascaded, whether the serial r om contains a single or multiple con guration pro- gr ams, etc. because of differing system requirements and capabilities, a single fpga/serial rom interface is generally not appropriate for all applications. data is read in the fpga sequentially from the serial r om. the data output from the serial rom is con- nected directly into the din input of the fpga. the cclk output from the fpga is connected to the clk input of the serial rom. during the con guration pro- cess, cclk clocks one data bit on each rising edge. since the data and clock are direct connects, the fpga/serial rom design task is to use the system or fpga to enable the reset /oe and ce of the serial r om(s). there are several methods for enabling the serial rom?s reset /oe and ce inputs. the serial r om?s reset /oe is programmable to function with reset active-high and oe active-low or reset active- low and oe active-high. in figure 39, serial roms are cascaded to con gure m ultiple daisy-chained fpgas. the host generates a 500 ns low pulse into the fpga's prgm input. the fpga?s init input is connected to the serial roms? reset /oe input, which has been programmed to function with reset active-low and oe active-high. the fpga done is routed to the ce pin. the low on done enables the serial roms. at the completion of con guration, the high on the fpgas done disables the serial rom. serial roms can also be cascaded to support the con- guration of multiple fpgas or to load a single fpga when con guration data requirements exceed the capacity of a single serial rom. after the last bit from the rst serial rom is read, the serial rom outputs ceo low and 3-states the data output. the next serial r om recognizes the low on ce input and outputs con- guration data on the data output. after con guration is complete, the fpga?s done output into ce disables the serial roms. this fpga/serial rom interface is not used in applica- tions in which a serial rom stores multiple con gura- tion programs. in these applications, the next con guration program to be loaded is stored at the r om location that follows the last address for the previ- ous con guration program. the reason the interface in figure 39 will not work in this application is that the low output on the init signal would reset the serial rom address pointer, causing the rst con guration to be reloaded. in some applications, there can be contention on the fpga's din pin. during con guration, din receives con guration data, and after con guration, it is a user i/o. if there is contention, an early done at start-up (selected in isplever) may correct the problem. an alternative is to use ldc to drive the serial rom's ce pin. in order to reduce noise, it is generally better to run the master serial con guration at 1.25 mhz (m3 pin tied high), rather than 10 mhz, if possible. one fpga in master serial mode can provide con gu- r ation data out on dout to additional fpgas in a daisy-chain con guration. the con guration data on dout is provided synchronously with the rising edge of cclk.
data sheet november, 2002 lattice semiconductor 67 orca series 4 fpgas fpga con guration modes (continued) note: m3 = gnd for high-speed cclk; m3 = v dd for low-frequency cclk. 5-4456(f).a figure 39. master serial con guration schematic din m2 m1 m0 orca series fpga cclk dout to daisy- chained devices d ata clk ce ceo d ata clk reset /oe ceo ce to more serial roms as needed done prgm pr ogram reset /oe asynchronous peripheral mode figure 40 shows the connections needed for the asyn- chronous peripheral mode. in this mode, the fpga system interface is similar to that of a microprocessor- peripheral interface. the microprocessor generates the control signals to write an 8-bit byte into the fpga. the fpga control inputs include active-low cs0 and active- high cs1 chip selects and wr and rd inputs. the chip selects can be cycled or maintained at a static level during the con guration cycle. each byte of data is writ- ten into the fpga?s d[7:0] input pins. d[7:0] of the fpga can be connected to d[7:0] of the microproces- sor only if a standard prom le format is used. if a .bit or .rbt le is used from isplever, then the user must mirror the bytes in the .bit or .rbt le or leave the .bit or .rbt le unchanged and connect d[7:0] of the fpga to d[0:7] of the microprocessor. the fpga provides an rdy/ b usy status output to indi- cate that another byte can be loaded. a low on rdy/ b usy indicates that the double-buffered hold/shift reg- isters are not ready to receive data, and this pin must be monitored to go high before another byte of data can be written. the shortest time rdy/ b usy is low occurs when a byte is loaded into the hold register and the shift register is empty, in which case the byte is immediately transferred to the shift register. the long- est time for rdy/ b usy to remain low occurs when a b yte is loaded into the holding register and the shift register has just started shifting con guration data into con guration ram. the rdy/ b usy status is also available on the d7 pin by enabling the chip selects, setting wr high, and apply- ing rd low, where the rd input provides an output enable for the d[7:3] when rd is low. the d[2:0] pins are not enabled to drive when rd is low and, therefore, only act as input pins in asynchronous peripheral mode. optionally, the user can ignore the rdy/ b usy status and simply wait until the maximum time it would take for the rdy/ b usy line to go high, indicating the fpga is ready for more data, before writing the next data byte. the following signals are also available on d[6:3] when wr is high and rd is low: d[6:5] is a 2-bit con guration bitstream error descrip- tion ag: 00= no error, 01 = id error, 10 = checksum error, 11 = stop bit/frame alignment error. d[4:3] is a 2-bit system bus error ag: 00 = no error, 01 = one error occurred, 11 = multiple errors occurred. one fpga in asynchronous peripheral mode can pro- vide con guration data out on dout to additional fpgas in a daisy-chain con guration. the con gura- tion data on dout is provided synchronously with the r ising edge of cclk.
68 lattice semiconductor data sheet november, 2002 orca series 4 fpgas fpga con guration modes (continued) note: m3 = gnd for high-speed cclk; m3 = v dd for low-frequency cclk. 5-9739(f).a figure 40. asynchronous peripheral con guration microprocessor interface mode the built-in mpi in series 4 fpgas is designed for use in con guring the fpga. figure 41 show the glueless inter- f ace for fpga con guration and readback from the po w erpc processor. when enabled by the mode pins, the mpi handles all con guration/readback control and handshaking with the host processor. for single fpga con gura- tion, the host sets the con guration control register mpi_prgm to one then back to zero and, after reading that the con guration write data acknowledge register is high, transfers data 8, 16, or 32 bits at a time to the fpga?s d[#:0] input pins. if con guring multiple fpgas through daisy-chain operation is desired, the sys_daisy bit must be set in the con guration control register of the mpi. the con guration control register offers control bits to enable the interrupt on a bit stream error. the mpi status register may be used in conjunction with, or in place of, the interrupt request option. the status register contains a 2-bit eld to indicate the bit stream error status. a ow chart of the mpi con guration process is shown in figure 42. micro- prgm orca series fpga dout cclk hdc ldc m2 m1 m0 v dd to daisy- chained devices processor d[7:0] rdy/busy init done address decode logic bus controller 8 cs0 cs1 rd wr
lattice semiconductor 69 data sheet november, 2002 orca series 4 fpgas fpga con guration modes (continued) 5-9738(f).b figure 41. po werpc /mpi con guration schematic con guration readback can also be performed via the mpi when it is in user mode. the mpi is enabled in user mode by setting the mp_user_enable bit to 1 in the con guration control register prior to the start of con gura- tion or through a con guration option. to perform readback, the host processor writes the 14-bit readback start address to the readback address registers and sets the sys_rd_cfg bit to one, then back to zero in the con gu- r ation control register. readback data is returned 8 bits at a time to the readback data register and is valid when the d at a_rdy bit of the status register is 1. there is no error checking during readback. a ow chart of the mpi read- back operation is shown in figure 43. the rd_data pin used for dedicated fpga readback is invalid during mpi readback. dout cclk d[0:n] ppc_a[14:31] mpi_clk mpi_rw mpi_ack mpi_bdip mpi_irq mpi_strb cs0 cs1 hdc ldc d[0:n] a[14:31] clkout rd/wr ta bdip irq x ts to daisy- chained devices powerpc orca 8, 16, 32 fpga series 4 done init bus controller dp[0:m] dp[0:m] 1, 2, 4 mpi_burst burst mpi_t ea t ea mpi_rtry retry mpi_tsz[0:1] tsz[0:1]
70 lattice semiconductor data sheet november, 2002 orca series 4 fpgas fpga con guration modes (continued) 5-5763(f) figure 42. con guration through mpi power on with write configuration read status register init = 1? no read status register bit stream error? data_rdy = 1? write data to done = 1? done error yes yes yes no no yes no valid m[3:0] control register bits configuration data reg write configuration data register
lattice semiconductor 71 data sheet november, 2002 orca series 4 fpgas fpga con guration modes (continued) 5-5764(f) figure 43. readback through mpi enable microprocessor set readback address write rd_cfg to 0 data_rdy = 1? read data register start of frame increment address data = 0xff? yes yes read status register in control register 1 interface in user mode read data register found? read until end of frame finished readback? counter in software yes yes write rd_cfg to 1 in control register 1 stop no no error no error no read data register data = 0xff? yes no error
72 lattice semiconductor data sheet november, 2002 orca series 4 fpgas fpga con guration modes (continued) slave serial mode the slave serial mode is primarily used when multiple fpgas are con gured in a daisy-chain (see the daisy- chaining section). it is also used on the fpga evaluation board that interfaces to the download cable. a device in the slave serial mode can be used as the lead device in a daisy-chain. figure 44 shows the connections for the slave serial con guration mode. the con guration data is provided into the fpga?s din input synchronous with the con guration clock cclk input. after the fpga has loaded its con guration data, it retransmits the incoming con guration data on dout at the ris- ing edge of cclk. cclk is routed into all slave serial mode devices in parallel. multiple slave fpgas can be loaded with identical con gurations simultaneously. this is done by loading the con- guration data into the din inputs in parallel. 5-4485(f).a figure 44. slave serial con guration schematic slave parallel mode the slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins d[7:0] for each cclk cycle. due to 8 bits of data being input per cclk cycle, the dout pin does not contain a v alid bit stream for slave parallel mode. as a result, the lead device cannot be used in the slave parallel mode in a daisy-chain con guration. figure 45 is a schematic of the connections for the slave parallel con guration mode. wr and cs0 are active-low chip select signals, and cs1 is an active-high chip select signal. these chip selects allow the user to con gure mul- tiple fpgas in slave parallel mode using an 8-bit data bus common to all of the fpgas. these chip selects can then be used to select the fpgas to be con gured with a given bit stream. the chip selects must be active for each v alid cclk cycle until the device has been completely programmed. they can be inactive between cycles but must meet the setup and hold times for each valid positive cclk. d[7:0] of the fpga can be connected to d[7:0] of the microprocessor only if a standard prom le format is used. if a .bit or .rbt le is used from isplever, then the user m ust mirror the bytes in the .bit or .rbt le or leave the .bit or .rbt le unchanged and connect d[7:0] of the fpga to d[0:7] of the microprocessor. micro- processor or download cable m2 m1 m0 hdc series fpga ldc v dd cclk prgm dout to daisy- chained devices done din init orca m3
lattice semiconductor 73 data sheet november, 2002 orca series 4 fpgas fpga con guration modes (continued) 5-4487(f).a figure 45. slave parallel con guration schematic daisy-chaining multiple fpgas can be con gured by using a daisy-chain of the fpgas. daisy-chaining uses a lead fpga and one or more fpgas con gured in slave serial mode. the lead fpga can be con gured in any mode except slave paral- lel mode. all daisy-chained fpgas are connected in series. each fpga reads and shifts the preamble and length count in on positive cclk and out on positive cclk edges. an upstream fpga that has received the preamble and length count outputs a high on dout until it has received the appropriate number of data frames so that downstream fpgas do not receive frame start indications. after loading and retransmitting the preamble and length count to a daisy-chain of slave devices, the lead device loads its con guration data frames. the loading of con guration data continues after the lead device has received its con g- uration data if its internal frame bit counter has not reached the length count. when the con guration ram is full and the number of bits received is less than the length count eld, the fpga shifts any additional data out on dout. the con guration data is read into din of slave devices on the positive edge of cclk, and shifted out dout on the positive edge of cclk. figure 46 shows the connections for loading multiple fpgas in a daisy-chain con guration. the generation of cclk for the daisy-chained devices that are in slave serial mode differs depending on the con g- uration mode of the lead device. a master parallel mode device uses its internal timing generator to produce an internal cclk at eight times its memory address rate (rclk). the asynchronous peripheral mode and mpi mode device outputs eight cclks for each write cycle. if the lead device is con gured in slave mode, cclk must be routed to the lead device and to all of the daisy-chained devices. micro- processor or system d[7:0] done cclk cs1 m2 m1 m0 hdc ldc 8 v dd init prgm cs0 wr series fpga orca m3
74 lattice semiconductor data sheet november, 2002 orca series 4 fpgas fpga con guration modes (continued) 5-4488(f).a figure 46. daisy-chain con guration schematic as seen in figure 46, the init pins for all of the fpgas are connected together. this is required to guarantee that powerup and initialization will work correctly. in general, the done pins for all of the fpgas are also connected together as shown to guarantee that all of the fpgas enter the start-up state simultaneously. this may not be required, depending upon the start-up sequence desired. daisy-chaining with boundary-scan multiple fpgas can be con gured through the jtag ports by using a daisy-chain of the fpgas. this daisy-chain- ing operation is available upon initial con guration after powerup, after a power-on reset, after pulling the program pin to reset the chip, or during a recon guration if the en_jtag ram has been set. all daisy-chained fpgas are connected in series. each fpga reads and shifts the preamble and length count in on the positive tck and out on the negative tck edges. an upstream fpga that has received the preamble and length count outputs a high on tdo until it has received the appropriate number of data frames so that downstream fpgas do not receive frame start bit pairs. after load- ing and retransmitting the preamble and length count to a daisy-chain of downstream devices, the lead device loads its con guration data frames. the loading of con guration data continues after the lead device had received its con guration read into tdi of downstream devices on the positive edge of tck, and shifted out tdo on the negative edge of tck. v dd eprom program oe ce m2 m1 m0 done hdc ldc rclk cclk dout din dout din cclk done dout init init init cclk v dd prgm prgm prgm hdc ldc rclk hdc ldc rclk v dd orca series fpga slave 2 orca series fpga master orca series fpga slave 1 a[21:0] a[21:0] d[7:0] d[7:0] done m3 m2 m1 m0 v dd m3 m2 m1 m0 v dd
lattice semiconductor 75 data sheet november, 2002 orca series 4 fpgas absolute ? maximum ? ratings stresses ? in ? excess ? of ? the ? absolute ? maximum ? ratings ? can ? cause ? permanent ? damage ? to ? the ? device. ? these ? are ? abso- lute ? stress ? ratings ? only. ? functional ? operation ? of ? the ? device ? is ? not ? implied ? at ? these ? or ? any ? other ? conditions ? in ? excess ? of ? those ? given ? in ? the ? operations ? sections ? of ? this ? data ? sheet. ? exposure ? to ? absolute ? maximum ? ratings ? for ? extended ? periods ? can ? adversely ? affect ? device ? reliability. the ? orca ? series ? fpgas ? include ? circuitry ? designed ? to ? protect ? the ? chips ? from ? damaging ? substrate ? injection ? currents ? and ? to ? prevent ? accumulations ? of ? static ? charge. ? nevertheless, ? conventional ? precautions ? should ? be ? observed ? during ? storage, ? handling, ? and ? use ? to ? avoid ? exposure ? to ? excessive ? electrical ? stress. t able ? 34. ? absolute ? maximum ? ratings recommended ? operating ? conditions t able ? 35. ? recommended ? operating ? conditions note: 1. the ? maximum ? recommended ? junction ? temperature ? (t j ) ? during ? operation ? is ? 125 ? c. ? 2. timing ? parameters ? in ? this ? data ? sheet ? an ? isplever ? are ? characterized ? under ? higher ? voltage ? and ? temperature ? conditions ? than ? the ? recom- mended ? operating ? conditions ? in ? this ? table. 3. the ? internal ? plls ? operate ? from ? the ? v dd 33 ? power ? supply. ? this ? power ? supply ? should ? be ? well ? isolated ? from ? all ? other ? power ? supplies ? on ? the ? board ? for ? proper ? operation. parameter symbol min max unit storage ? t emperature t stg ?65 150 c power ? supply ? v oltage ? with ? respect ? to ? ground v dd 33 ?0.3 4.2 v v dd io ?0.3 4.2 v v dd 15 ?0.3 2.0 v input ? signal ? with ? respect ? to ? ground v in ? ? 0.3 v dd io ? + ? 0.3 v signal ? applied ? to ? high-impedance ? output ? ? ? 0.3 v dd io ? + ? 0.3 v maximum ? package ? body ? (soldering) ? t emperature ? ? 220 c parameter symbol min max unit power ? supply ? v oltage ? with ? respect ? to ? ground v dd 33 3.0 3.6 v v dd io 1.4 3.6 v v dd 15 1.425 1.575 v input ? signal ? with ? respect ? to ? ground v in ? ? 0.3 v dd io ? + ? 0.3 v junction ? t emperature t j ?40 125 c
76 lattice semiconductor data sheet november, 2002 orca series 4 fpgas electrical ? characteristics t able ? 36. ? electrical ? characteristics or4exx ? industrial: ? v dd 15 ? = ? 1.4 ? v ? to ? 1.6 ? v, ? v dd 33 ? = ? 3.0 ? v ? to ? 3.6 ? v, ? v dd io ? = ? 3.0 ? v ? to ? 3.6 ? v, ? ?40 ? c ? < ? t a ? < ? +125 ? c; c l ? = ? 30 ? pf . * the ? pull-up ? resistor ? will ? externally ? pull ? the ? pin ? to ? a ? level ? 1.0 ? v ? below ? v dd io. note: 1. ? the ? standby ? current ? for ? v dd io ? is ? variable ? depending ? upon ? i/o ? types. ? for ? l vttl ? i/o ? held ? at ? v dd io ? or ? gnd, ? this ? value ? is ? typically ? less ? than ? 1 ? ma. parameter symbol test ? conditions or4exx unit min typ max input ? leakage ? current i l v dd io ? = ? max, ? v in ? = ? v ss ? or ? v dd io ? ? 10 ? 10 a standby ? current ? (v dd 15 ): or4e02 or4e04 or4e06 i dd sb15 t a ? = ? 25 ? c, ? v dd 15 ? = ? 1.6 ? v, ? v dd 33 ? = ? 3.6 ? v, ? v dd io ? = ? 3.6 ? v, internal ? oscillator ? running, ? no ? output ? loads, inputs ? v dd io ? or ? v ss ? (after ? configuration) ? ? ? 5 10 15 200 200 200 ma ma ma same ? conditions ? except ? t a ? = ? 85 ? c ? ? 500 ma standby ? current ? (v dd 33 ) : or4e02 or4e04 or4e06 i dd sb33 t a ? = ? 25 ? c, ? v dd 15 ? = ? 1.6 ? v, ? v dd 33 ? = ? 3.6 ? v, ? v dd io ? = ? 3.6 ? v, internal ? oscillator ? stopped, ? no ? output ? loads, inputs ? v dd io ? or ? gnd ? (after ? configuration) ? ? ? 4 7 10 100 100 100 ma ma ma same ? conditions ? except ? t a ? = ? 85 ? c ? ? 300 ma data ? retention ? v oltage ? (v dd 33 ) v dr 33 t j ? = ? ?40 ? c ? to ? 125 ? c 2.3 ? ? v data ? retention ? v oltage ? (v dd 15 ) v dr 15 t j ? = ? ?40 ? c ? to ? 125 ? c 1.1 ? ? v dc ? input ? levels v il v ih input ? levels ? vary ? per ? input ? standard. ? see ? the ? series ? 4 ? io ? application ? note ? for ? details v arious ? various v dc ? output ? levels v ol v oh output ? levels ? vary ? per ? output ? standard. ? see ? the ? series ? 4 ? io ? application ? note ? for ? details v arious ? various v output ? drive ? currents i ol i oh output ? currents ? vary ? per ? output ? standard. ? see ? the ? series ? 4 ? io ? application ? note ? for ? details v arious ? various ma input ? capacitance c in t a ? = ? 25 ? c, ? v dd io ? = ? 3.6 ? v, t est ? frequency ? = ? 1 ? mhz ?? 5pf output ? capacitance c out t a ? = ? 25 ? c, ? v dd io ? = ? 3.6 ? v, t est ? frequency ? = ? 1 ? mhz ?? 5pf done ? pull-up ? resistor* r done v dd io ? = ? 3.0 ? v ? to ? 3.6 ? v, ? v in ? = ? v ss , ? t j ? = ? ?40 ? c ? to ? 125 ? c 100 ? ? k ? m[3:0] ? pull-up ? resistors* r m v dd io ? = ? 3.0 ? v ? to ? 3.6 ? v, ? v in ? = ? v ss , ? t j ? = ? ?40 ? c ? to ? 125 ? c 100 ? ? k ? i/o ? pad ? static ? pull-up ? current* i pu v dd io ? = ? 3.0 ? v ? to ? 3.6 ? v, ? v in ? = ? v ss , ? t j ? = ? ?40 ? c ? to ? 125 ? c 14.4 ? 50.9 a i/o ? pad ? static ? pull-down ? current i pd v dd io ? = ? 3.0 ? v ? to ? 3.6 ? v, ? v in ? = ? v ss , ? t j ? = ? ?40 ? c ? to ? 125 ? c 26 ? 103 a i/o ? pad ? pull-up ? resistor* r pu v dd io ? = ? 3.0 ? v ? to ? 3.6 ? v, ? v in ? = ? v ss , ? t j ? = ? ?40 ? c ? to ? 125 ? c 100 ? ? k ? i/o ? pad ? pull-down ? resistor r pd v dd io ? = ? 3.0 ? v ? to ? 3.6 ? v, ? v in ? = ? v dd , ? t j ? = ? ?40 ? c ? to ? 125 ? c 50 ? ? k ?
lattice semiconductor 77 data sheet november, 2002 orca series 4 fpgas power ? estimation a spreadsheet is available in isplever for detailed power estimates based on circuit implementation details from isplever and user inputs. a quick esti- mate of power dissipation for a series 4 device is now presented. estimating power dissipation the total operating power dissipated is estimated by adding the standby (i dd sb), internal, and external power dissipated. the internal and external power is the power consumed in the plcs and pics, respec- tively. in general, the standby power is small and may be neglected. the total operating power is as follows: p t = p int + p io + p clk the internal operating power is made up of two parts: clock generation and pfu/ebr/pio power. the pfu/ ebr/pio power can be estimated per output based upon the number of pfu/ebr/pio outputs switching when driving a typical fanout (three x6 lines and nine x1 lines). p int = 0.015 mw/mhz f or each pfu/ebr/pio output that switches, 0.015 mw/mhz needs to be multiplied times the frequency (in mhz) that the output switches. generally, this can be estimated by using the clock rate multiplied by some activity factor; for example, 20%. the power dissipated by clocks is due to either global primary clock networks or secondary/edge clock net- wo rk s. their power has a x ed component and a vari- able component based on the number of pfus, pios, or ebrs that use that clock as follows: primary: 0.143 mw/mhz + (0.0033mw/mhz x num- ber of blocks driven) secondary: 0.06 mw/mhz + (0.0029mw/mhz x n umber of blocks driven) clock power is calculated from these equations by mul- tiplying times the clock frequency in mhz. note that an activity factor (i.e., 100% activity) is not used to calcu- late clock power. the device i/o power dissipated is the sum of the power dissipated in the four pios in the pic. this con- sists of power dissipated by inputs and ac power dissi- pated by outputs. the power dissipated in each pio depends on whether it is con gured as an input, out- put, or input/output. if a pio is operating as an output, then there is a power dissipation component for p in , as w ell as p out . this is because the output feeds back to the input. the power dissipated by a lvcmos2 input buffer is (v ih = v dd ? 0.3 v or higher) estimated as: p in = 0.09 mw/mhz the ac power dissipation from a lvcmos2 output or bidirectional is estimated by the following: p out = (c l + 5.0 pf) x v dd 2 x f watts where the unit for c l (the output capacitive load) is far- ads, and the unit for f is hz. f or all other i/o buffer types other than lvcmos2, see the detailed power estimation spreadsheet available in isplever.
78 lattice semiconductor data sheet november, 2002 orca series 4 fpgas t iming ? characteristics to ? define ? speed ? grades, ? the ? orca ? series ? part ? number ? designation ? (see ? ordering ? information) ? uses ? a ? single-digit ? number ? to ? designate ? a ? speed ? grade. ? this ? number ? is ? not ? related ? to ? any ? single ? ac ? parameter. ? higher ? numbers ? indi- cate ? a ? faster ? set ? of ? timing ? parameters. ? the ? actual ? speed ? sorting ? is ? based ? on ? testing ? the ? delay ? in ? a ? path ? consisting ? of ? an ? input ? buffer, ? combinatorial ? delay ? through ? all ? plcs ? in ? a ? row, ? and ? an ? output ? buffer. ? other ? tests ? are ? then ? done ? to ? verify ? other ? delay ? parameters, ? such ? as ? routing ? delays, ? setup ? times ? to ? ffs, ? etc. the ? most ? accurate ? timing ? characteristics ? are ? reported ? by ? the ? timing ? analyzer ? in ? isplever? ? design ? software. ? a ? timing ? report ? provided ? by ? the ? development ? system ? after ? layout ? divides ? path ? delays ? into ? logic ? and ? routing ? delays. ? the ? timing ? analyzer ? can ? also ? provide ? logic ? delays ? prior ? to ? layout. ? while ? this ? allows ? routing ? budget ? estimates, ? there ? is ? wide ? variance ? in ? routing ? delays ? associated ? with ? different ? layouts. ? the ? logic ? timing ? parameters ? noted ? in ? the ? electrical ? characteristics ? section ? of ? this ? data ? sheet ? are ? the ? same ? as ? those ? in ? isplever. ? in ? the ? timing ? tables ? that ? follow, ? symbol ? names ? are ? generally ? a ? concatenation ? of ? the ? pfu ? operating ? mode ? (as ? defined ? in ? t able ? 3) ? and ? the ? parameter ? type. ? the ? setup, ? hold, ? and ? propagation ? delay ? parameters, ? defined ? below, ? are ? designated ? in ? the ? symbol ? name ? by ? the ? set, ? hld, ? and ? del ? characters, ? respectively. ? the ? values ? given ? for ? the ? parameters ? are ? the ? same ? as ? those ? used ? during ? production ? testing ? and ? speed ? binning ? of ? the ? devices. ? the ? junction ? temperature ? and ? supply ? voltage ? used ? to ? characterize ? the ? devices ? are ? listed ? in ? the ? delay ? tables ? and ? the ? delay ? values ? in ? this ? data ? sheet ? are ? from ? isplever. ? actual ? delays ? at ? nominal ? temperature ? and ? voltage ? for ? best-case ? processes ? can ? be ? much ? better ? than ? the ? values ? given. ? it ? should ? be ? noted ? that ? the ? junction ? temperature ? used ? in ? the ? tables ? is ? generally ? 85 ? c ? or ? 100 ? c, ? based ? on ? the ? tem- perature ? grade ? of ? the ? device. ? the ? junction ? temperature ? for ? the ? fpga ? depends ? on ? the ? power ? dissipated ? by ? the ? device, ? the ? package ? thermal ? characteristics ? ( ja ), ? and ? the ? ambient ? temperature, ? as ? calculated ? in ? the ? following ? equation ? and ? as ? discussed ? further ? in ? the ? package ? thermal ? characteristics ? section: t jmax ? = ? t amax ? + ? (p ? ? ? ja ) ? c note : the ? user ? must ? determine ? this ? junction ? temperature ? to ? see ? if ? the ? delays ? from ? isplever ? should ? be ? derated ? based ? on ? the ? following ? derating ? tables. t able ? 37?table ? 38 ? provide ? approximate ? power ? supply ? and ? junction ? temperature ? derating ? for ? series ? 4 ? commercial ? and ? industrial ? devices. ? the ? delay ? values ? in ? this ? data ? sheet ? and ? reported ? by ? isplever ? are ? shown ? as ? 1.00 ? in ? the ? tables. ? the ? method ? for ? determining ? the ? maximum ? junction ? temperature ? is ? defined ? in ? the ? package ? thermal ? charac- teristics ? section. ? t aken ? cumulatively, ? the ? range ? of ? parameter ? values ? for ? best-case ? vs. ? worst-case ? processing, ? sup- ply ? voltage, ? and ? junction ? temperature ? can ? approach ? 3 ? to ? 1. the ? typical ? timing ? path ? in ? series ? 4 ? is ? made ? up ? of ? both ? 3.3 ? v ? (v dd io ? and/or ? v dd 33) ? components ? and ? 1.5 ? v ? (v dd 15) ? components. ? for ? example, ? all ? i/o ? circuits ? use ? v dd io ? at ? the ? device ? interface ? but ? all ? internal ? routing ? and ? i/o ? register ? logic ? use ? v dd 15. ? thus ? actual ? voltage ? derating ? needs ? to ? be ? done ? based ? on ? multiple ? parameters. ? a ? simple ? approxi- mation ? is ? that ? 50% ? of ? the ? delay ? path ? is ? due ? to ? each ? of ? these ? parameters. ? all ? internal ? paths ? use ? v dd 15 ? for ? logic ? and ? v dd 33 ? for ? routing, ? but ? if ? v dd 33 ? remains ? above ? 3.0 ? v ? the ? internal ? delays ? can ? be ? assumed ? to ? be ? dependent ? on ? v dd 15 ? derating ? values ? only. ? note ? however ? that ? temperature ? derating ? is ? approximately ? the ? same ? percentage ? for ? all ? three ? supply ? voltages ? thus ? allowing ? one ? temperature ? derating ? value ? to ? be ? used. ? for ? the ? most ? accurate ? results, ? volt- age ? and ? temperature ? derating ? capabilities ? to ? be ? released ? in ? isplever ? should ? be ? used.
lattice semiconductor 79 data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) ta b le 37. i/o derating for 3.3 v i/os (v dd io)?only valid for ttl/cmos i/os t able ? 38. ? internal ? derating ? for ? 1.5v ? (v dd 15) in ? addition ? to ? supply ? voltage, ? process ? variation, ? and ? operating ? temperature, ? circuit ? and ? process ? improvements ? of ? the ? orca ? series ? fpgas ? over ? time ? will ? result ? in ? significant ? improvement ? of ? the ? actual ? performance ? over ? those ? listed ? for ? a ? speed ? grade. ? even ? though ? lower ? speed ? grades ? may ? still ? be ? available, ? the ? distribution ? of ? yield ? to ? timing ? param- eters ? may ? be ? several ? speed ? grades ? higher ? than ? that ? designated ? on ? a ? product ? brand. ? design ? practices ? need ? to ? con- sider ? best-case ? timing ? parameters ? (e.g., ? delays ? = ? 0), ? as ? well ? as ? worst-case ? timing. the ? routing ? delays ? are ? a ? function ? of ? fan-out ? and ? the ? capacitance ? associated ? with ? the ? cips ? and ? metal ? interconnect ? in ? the ? path. ? the ? number ? of ? logic ? elements ? that ? can ? be ? driven ? (fan-out) ? by ? pfus ? is ? unlimited, ? although ? the ? delay ? to ? reach ? a ? valid ? logic ? level ? can ? exceed ? timing ? requirements. ? it ? is ? difficult ? to ? make ? accurate ? routing ? delay ? estimates ? prior ? to ? design ? compilation ? based ? on ? fan-out. ? this ? is ? because ? the ? cae ? software ? may ? delete ? redundant ? logic ? inserted ? by ? the ? designer ? to ? reduce ? fan-out, ? and/or ? it ? may ? also ? automatically ? reduce ? fan-out ? by ? net ? splitting. the ? waveform ? test ? points ? are ? given ? in ? the ? input/output ? buffer ? measurement ? conditions ? section ? of ? this ? data ? sheet. ? the ? timing ? parameters ? given ? in ? the ? electrical ? characteristics ? tables ? in ? this ? data ? sheet ? follow ? industry ? practices, ? and ? the ? values ? they ? reflect ? are ? described ? below. ? t j ? (c) commercial t j ? (c) industrial power ? supply ? v oltage 3.0 ? v 3.15 ? v 3.3 ? v 3.45 ? v 3.6 ? v ? ?40 0.82 0.80 0.77 0.75 0.74 ?40 ?25 0.83 0.81 0.78 0.76 0.75 015 0.87 0.84 0.81 0.80 0.78 25 40 0.91 0.88 0.85 0.82 0.81 85 100 1.00 0.97 0.93 0.91 0.88 100 115 1.02 0.99 0.96 0.93 0.90 110 125 1.05 1.01 0.97 0.95 0.92 125 ? 1.07 1.03 0.99 0.97 0.94 t j ? (c) commercial t j ? (c) industrial power ? supply ? v oltage 1.40 ? v 1.425 ? v 1.500 ? v 1.575 ? v 1.6 ? v ? ?40 0.87 0.85 0.82 0.79 0.78 ?40 ?25 0.89 0.87 0.83 0.80 0.79 015 0.93 0.91 0.87 0.82 0.81 25 40 0.96 0.94 0.89 0.85 0.84 85 100 1.02 1.00 0.95 0.91 0.90 100 115 1.04 1.02 0.97 0.93 0.92 110 125 1.05 1.03 0.98 0.94 0.93 125 ? 1.06 1.05 1.00 0.96 0.95
80 lattice semiconductor data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) propagation ? delay ?the ? time ? between ? the ? specified ? reference ? points. ? the ? delays ? provided ? are ? the ? worst ? case ? of ? the ? tphh ? and ? tpll ? delays ? for ? noninverting ? functions, ? tplh ? and ? tphl ? for ? inverting ? functions, ? and ? tphz ? and ? tplz ? for ? 3-state ? enable. setup ? t ime ?the ? interval ? immediately ? preceding ? the ? transition ? of ? a ? clock ? or ? latch ? enable ? signal, ? during ? which ? the ? data ? must ? be ? stable ? to ? ensure ? it ? is ? recognized ? as ? the ? intended ? value. hold ? t ime ?the ? interval ? immediately ? following ? the ? transition ? of ? a ? clock ? or ? latch ? enable ? signal, ? during ? which ? the ? data ? must ? be ? held ? stable ? to ? ensure ? it ? is ? recognized ? as ? the ? intended ? value. 3-state ? enable ?the ? time ? from ? when ? a ? 3-state ? control ? signal ? becomes ? active ? and ? the ? output ? pad ? reaches ? the ? high-impedance ? state. ? ta b le 39. pfu timing parameters or4exx commercial: vdd15 = 1.425 v, vdd33 = 3.0 v, tj = +85 ? c or4exx industrial: vdd15 = 1.425 v, vdd33 = 3.0 v, tj = +100 ? c note: ? a complete listing of pfu timing parameters can be displayed in isplever. this is a sampling of the key timing parameters. parameter symbol speed unit ?1 ?2 ?3 min max min max min max combinatorial delays: f our-input variables to lut out five-input variables to lut out six-input variables to lut out f4_del f5_del f6_del ? ? ? 0.66 0.77 1.10 ? ? ? 0.55 0.64 0.81 ? ? ? 0.50 0.58 0.74 ns ns ns sequential delays: clk low time clk high time f our-input variables to register clk setup five-input variables to register clk setup six-input variables to register clk setup data in to register clk setup f our-input variables from register clk hold five-input variables from register clk hold six-input variables from register clk hold data in from register clk hold register clk to out clkl_mpw clkh_mpw f4_set f5_set f6_set din_set f4_hld f5_hld f6_hld din-hld reg_del 0.36 0.40 0.28 0.38 0.71 0.00 0.00 0.10 0.00 0.25 1.03 ? ? ? ? ? ? ? ? ? ? ? 0.35 0.38 0.23 0.28 0.63 0.00 0.00 0.16 0.10 0.24 0.92 ? ? ? ? ? ? ? ? ? ? ? 0.32 0.35 0.21 0.25 0.57 0.00 0.00 0.15 0.09 0.22 0.84 ? ? ? ? ? ? ? ? ? ? ? ns ns ns ns ns ns ns ns ns ns ns pfu clk to out (reg_del) delay adjustments from cycle stealing: one delay cell tw o delay cells three delay cells cycdel1 cycdel2 cycdel3 0.89 1.64 2.43 ? ? ? 0.70 1.29 1.98 ? ? ? 0.64 1.18 1.80 ? ? ? ns ns ns
lattice semiconductor 81 data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) t able ? 40. ? pfu ? used ? as ? dual-port ? ram: ? sync. ? w rite ? and ? sync. ? or ? async. ? read ? t iming ? characteristics or4exx commercial: vdd15 = 1.425 v, vdd33 = 3.0 v, tj = +85 ? c or4exx industrial: vdd15 = 1.425 v, vdd33 = 3.0 v, tj = +100 ? c note: ? a ? complete ? listing ? of ? pfu ? timing ? parameters ? can ? be ? displayed ? in ? isplever. ? this ? is ? a ? sampling ? of ? the ? key ? timing ? parameters. ? parameter symbol speed unit -1 -2 -3 min max min max min max write operation for ram mode: maximum write clock frequency write data to clk setup time write clk to data out smwclk_frq wd_set mem_del ? 0.32 ? 300.00 ? 2.21 ? 0.24 ? 382.00 ? 1.89 ? 0.22 ? 422.00 ? 1.71 mhz ns ns async read operation for ram mode: data out valid after address ra_del ? 0.66 ? 0.55 ? 0.50 ns sync read operation for ram mode: maximum read clock frequency read clk to data out smrclk_frq reg_del ? ? 300.00 1.03 ? ? 382.00 0.92 ? ? 422.00 0.84 mhz ns
82 lattice semiconductor data sheet november, 2002 orca series 4 fpgas timing characteristics (continued) t able ? 41. ? embedded ? block ? ram ? (ebr) ? t iming ? characteristics ? (512 ? x ? 18) ? quad-port ? ram ? mode or4exx commercial: vdd15 = 1.425 v, vdd33 = 3.0 v, tj = +85 ? c or4exx industrial: vdd15 = 1.425 v, vdd33 = 3.0 v, tj = +100 ? c note: a ? complete ? listing ? of ? ebr ? t iming ? parameters ? can ? be ? displayed ? in ? isplever. ? this ? is ? a ? sampling ? of ? the ? key ? timing ? parameters. ta b le 42. supplemental logic and interconnect cell (slic) timing characteristics or4exx commercial: vdd15 = 1.425 v, vdd33 = 3.0 v, tj = +85 ? c or4exx industrial: vdd15 = 1.425 v, vdd33 = 3.0 v, tj = +100 ? c note: a ? complete ? listing ? of ? slic ? t iming ? parameters ? can ? be ? displayed ? in ? isplever. ? this ? is ? a ? sampling ? of ? the ? key ? timing ? parameters. parameter symbol speed unit -1 -2 -3 min max min max min max write operation for ram mode: maximum write clock frequency write data to write clock setup time write address to write clock setup time ebrwclk_frq d*_ckw*_set a*_ckw*_set ? 0.28 0.40 200.0 ? ? ? 0.31 0.38 217.0 ? ? ? 0.28 0.35 225.0 ? ? mhz ns ns async read operation for ram mode: data out valid after read address ebr_ra_del ? 6.38 ? 6.00 ? 5.46 ns sync read operation for ram mode: maximum read clock frequency read address to read clock setup time (outreg mode) read clock to data out (ioreg or out- reg modes) ebrrclk_frq ar*_ckr*_set ckr*_q*_del ? ? ? 200.0 3.61 3.05 ? ? ? 217.0 3.45 2.84 ? ? ? 225.0 3.13 2.59 mhz ns ns parameter symbol speed unit -1 -2 -3 min max min max min max 3-statable bidis bidi buffer delay bidi 3-state enable/disable delay b uf_del tri_del ? ? 0.35 0.39 ? ? 0.35 0.35 ? ? 0.32 0.32 ns ns decoder decoder delay (br[9:8], bl[9:8] to dec) dec_del ? 0.89 ? 0.81 ? 0.73 ?
lattice semiconductor 83 data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) t able ? 43. ? pio ? input ? buffer ? t iming ? characteristics or4exx commercial: vdd15 = 1.425 v, vdd33 = 3.0 v, vddio = min, tj = +85 ? c or4exx industrial: vdd15 = 1.425 v, vdd33 = 3.0 v, vddio = min, tj = +100 ? c notes: the ? delays ? for ? all ? input ? buffers ? assume ? an ? input ? rise/fall ? time ? of ? < 1 ? v/ns. the ? values ? in ? the ? above ? table ? should ? be ? used ? to ? modify ? the ? results ? all ? information ? in ? the ? following ? system ? timing ? tables, ? which ? are ? all ? based ? on ? l vttl ? input ? timing. parameter symbol speed unit -1 -2 -3 min max min max min max input ? delays input rise time in_ris ? 100 ? 100 ? 100 ns input fall time in_fal ? 100 ? 100 ? 100 ns input delay adjustments from lvttl: l vcmos2 (2.5 v) l vcmos18 (1.8 v) l vds l vpecl pci_33 (3.3 v) pci_66 (3.3 v) gtl gtlp (gtl+) hstl_i hstl_ii hstl_iii hstl_iv sstl2_i sstl2_ii sstl3_i sstl3_ii pecl in_lvcmos25 in_lvcmos15 in_lvds in_lvpecl in_pci_33 in_pci_66 in_gtl in_gtlp in_hstl_i in_hstl_ii in_hstl_iii in_hstl_iv in_sstl2_i in_sstl2_ii in_sstl3_i in_sstl3_ii in_pecl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0.54 1.91 ?0.04 ?0.31 0.59 0.59 5.32 1.87 ?0.05 ?0.05 ?0.20 ?0.20 2.28 2.28 0.78 0.78 0.83 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0.44 1.50 0.10 ?0.21 0.50 0.50 4.68 2.04 ?0.06 ?0.06 ?0.13 ?0.13 1.66 1.66 0.69 0.69 0.72 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0.40 1.36 0.09 ?0.19 0.45 0.45 4.26 1.86 ?0.06 ?0.06 ?0.12 ?0.12 1.51 1.51 0.63 0.63 0.65 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
84 lattice semiconductor data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) t able ? 44. ? pio ? output ? buffer ? t iming ? characteristics ? or4exx commercial: vdd15 = 1.425 v, vdd33 = 3.0 v, vddio = min, tj = +85 ? c or4exx industrial: vdd15 = 1.425 v, vdd33 = 3.0 v, vddio = min, tj = +100 ? c * see ? the ? series ? 4 ? pio ? application ? note ? for ? output ? load ? conditions ? on ? these ? output ? buffer ? types. note: the ? values ? in ? the ? above ? table ? should ? be ? used ? to ? modify ? the ? results ? all ? information ? in ? the ? following ? system ? timing ? tables, ? which ? are ? all ? based ? on ? 12 ? ma ? fast ? ttl ? (olvttl_f12) ? output ? timing. parameter symbol speed unit output load (pf) -1 -2 -3 min max min max min max output ? delays output delay adjustments from olvttl_f12: l vttl_s6 (slew limited, 6 ma) out_lvttl_s6 ? 2.01 ? 1.72 ? 1.56 ns 30 pf l vttl_s12 (slew limited, 12 ma) out_lvttl_s12 ? 1.25 ? 1.06 ? 0.97 ns 30 pf l vttl_s24 (slew limited, 24 ma) out_lvttl_s24 ? 0.76 ? 0.60 ? 0.55 ns 30 pf l vttl_f6 (fast, 6 ma) out_lvttl_f6 ? 0.72 ? 0.68 ? 0.61 ns 30 pf l vttl_f24 (fast, 24 ma) out_lvttl_f24 ? ?0.35 ? ?0.32 ? ?0.29 ns 30 pf l vcmos18_s6 (slew limited, 6 ma) out_cmos18_s6 ? 6.91 ? 5.36 ? 4.87 ns 30 pf l vcmos18_s12 (slew limited, 12 ma) out_cmos18_s12 ? 6.23 ? 3.90 ? 3.55 ns 30 pf l vcmos18_s24 (slew limited, 24 ma) out_cmos18_s24 ? 4.50 ? 3.29 ? 2.99 ns 30 pf l vcmos18_f6 (fast, 6 ma) out_cmos18_f6 ? 4.75 ? 3.83 ? 3.48 ns 30 pf l vcmos18_f12 (fast, 12 ma) out_cmos18_f12 ? 2.38 ? 1.86 ? 1.69 ns 30 pf l vcmos18_f24 (fast, 24 ma) out_cmos18_f24 ? 1.23 ? 0.90 ? 0.82 ns 30 pf l vcmos2_s6 (slew limited, 6 ma) out_cmos18_s6 ? 3.26 ? 2.66 ? 2.42 ns 30 pf l vcmos2_s12 (slew limited, 12 ma) out_cmos18_s12 ? 2.09 ? 1.69 ? 1.54 ns 30 pf l vcmos2_s24(slew limited, 24 ma) out_cmos18_s24 ? 1.58 ? 1.23 ? 1.12 ns 30 pf l vcmos2_f6 (fast, 6 ma) out_cmos18_f6 ? 1.80 ? 1.59 ? 1.44 ns 30 pf l vcmos2_f12 (fast, 12 ma) out_cmos18_f12 ? 0.61 ? 0.50 ? 0.45 ns 30 pf l vcmos2_f24 (fast, 24 ma) out_cmos18_f24 ? 0.03 ? ?0.03 ? ?0.03 ns 30 pf l vds out_lvds ? 0.07 ? 0.00 ? 0.00 ns * l vpecl out_lvpecl ? ?0.57 ? ?0.55 ? ?0.50 ns * pci_33 (3.3v) out_pci_33 ? 4.84 ? 3.42 ? 3.11 ns 10 pf pci_66 (3.3v) out_pci_66 ? 4.84 ? 3.42 ? 3.11 ns 10 pf gtl out_gtl ? 3.22 ? 2.45 ? 2.23 ns * gtlp (gtl+) out_gtlp ? 3.60 ? 2.76 ? 2.51 ns * hstl_i out_hstl_i ? 1.89 ? 1.30 ? 1.18 ns 20 pf hstl_ii out_hstl_ii ? 1.89 ? 1.30 ? 1.18 ns 20 pf hstl_iii out_hstl_iii ? 2.78 ? 1.78 ? 1.62 ns 20 pf hstl_iv out_hstl_iv ? 2.78 ? 1.78 ? 1.62 ns 20 pf sstl2_i out_sstl2_i ? ?0.15 ? ?0.18 ? ?0.16 ns 30 pf sstl2_ii out_sstl2_ii ? ?0.15 ? ?0.18 ? ?0.16 ns 30 pf sstl3_i out_sstl3_i ? ?0.50 ? ?0.41 ? ?0.37 ns 30 pf sstl3_ii out_sstl3_ii ? ?0.50 ? ?0.41 ? ?0.37 ns 30 pf pecl out_pecl ? 0.12 ? 0.16 ? 0.15 ns 25 pf output ? delay ? adjustments ? from ? cycle ? stealing ? (typically ? used ? to ? adjust ? setup ? vs. ? clk->out): one ? delay ? cell ocycdel1 0.89 ? 0.70 ? 0.64 ? ns ? two ? delay ? cells ocycdel2 1.64 ? 1.29 ? 1.18 ? ns ? three ? delay ? cells ocycdel3 2.43 ? 1.98 ? 1.80 ? ns ?
lattice semiconductor 85 data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) t able ? 45. ? microprocessor ? interface ? (mpi) ? t iming ? characteristics or4exx commercial/industrial: vdd15 = 1.4 v to 1.6 v, vdd33 = 3.0 v to 3.6 v, vddio= 3.0 v to 3.6 v, ?40 c < tj ? < + 125 c t able ? 46. ? embedded ? system ? bus ? (esb) ? t iming ? characteristics or4exx commercial/industrial: vdd15 = 1.4 v to 1.6 v, vdd33 = 3.0 v to 3.6 v, vddio= 3.0 v to 3.6 v, ?40 c < tj ? < + 125 c t able ? 47. ? phase-locked ? loop ? (pll) ? t iming ? characteristics see the section on plls in this data sheet and in the pll application note for timing information. t able ? 48. ? boundary-scan ? t iming ? characteristics ? or4exx commercial/industrial: vdd15 = 1.4 v to 1.6 v, vdd33 = 3.0 v to 3.6 v, vddio= 3.0 v to 3.6 v, ?40 c < tj ? < +125 c; cl = 30 p f. 5-6764(f) figure ? 47. ? boundary-scan ? t iming ? diagram ? parameter symbol min max unit mpi ? control ? (strb, ? wr, ? etc.) ? to ? mpi_clk ? setup ? t ime mpictrl_set 7.7 ? ns mpi ? address ? to ? mpi_clk ? setup ? t ime mpiadr_set 3.5 ? ns mpi ? w rite ? data ? to ? mpi_clk ? setup ? t ime mpidat_set 3.4 ? ns all ? hold ? t imes mpi_hld 0.0 ? ns mpi_clk ? to ? mpi ? control ? (ta, ? tea, ? retry) mpictrl_del ? 8.3 ns mpi_clk ? to ? mpi ? data ? (8-bit) mpidat8_del ? 9.2 ns mpi_clk ? to ? mpi ? data ? (16-bit) mpidat16_del ? 10.0 ns mpi_clk ? to ? mpi ? data ? (32-bit) mpidat32_del ? 10.6 ns mpi_clk ? frequency mpi_clk_frq ? 66 mhz parameter symbol min max unit esb_clk ? frequency ? (no ? wait ? states) esb_clk ? frequency ? (with ? wait ? states) esb_clk_frq esb_clk_frq ? ? 66 100 mhz mhz parameter symbol min max unit tdi/tms ? to ? tck ? setup ? t ime t s 10.0 ? ns tdi/tms ? hold ? t ime ? from ? tck t h 0.0 ? ns tck ? low ? t ime t cl 25.0 ? ns tck ? high ? t ime t ch 25.0 ? ns tck ? to ? tdo ? delay t d ? 10.0 ns tck ? frequency t tck ? 20.0 mhz tck tms tdi tdo t s t h t d
86 lattice semiconductor data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) ? t able ? 49. ? primary ? clock ? skew ? to ? any ? pfu ? or ? pio ? register or4exx commercial/industrial: vdd15 = 1.425 v to 1.575 v, vdd33 = 3.0 v to 3.6 v, ?40 c < tj < +125 c . t able ? 50. ? secondary ? clock ? to ? output ? delay ? without ? on-chip ? plls ? (pin-to-pin) ? or4exx commercial: vdd15 = 1.425 v to 1.575 v, vdd33 = 3.0 v to 3.6 v, vddio = 3.0 v to 3.6 v, ?40 c < tj ? < +85 c.; cl = 30 pf or4exx industrial: vdd15 = 1.425 v to 1.575 v, vdd33 = 3.0 v to 3.6 v, vddio = 3.0 v to 3.6 v, ?40 c < tj ? < +100 c.; cl = 30 pf. notes: ? 1. timing ? is ? without ? the ? use ? of ? the ? phase-locked ? loops ? (plls). 2. this ? clock ? delay ? is ? for ? a ? fully ? routed ? clock ? tree ? that ? uses ? the ? secondary ? clock ? network. ? it ? includes ? the ? l vttl ? (3.3 ? v) ? input ? clock ? buffer, ? the ? clock ? routing ? to ? the ? pio ? clk ? input, ? the ? clock q ? of ? the ? ff, ? and ? the ? delay ? through ? the ? l vttl ? (3.3 ? v) ? data ? output ? buffer. ? an ? sclk ? input ? clock ? can ? be ? at ? any ? input ? pin. 3. for ? timing ? improvements ? using ? other ? i/o ? buffer ? types ? for ? the ? input ? clock ? buffer ? or ? output ? data ? buffer, ? see ? t able ? 45 ? and ? t able ? 47. 5-4846(f).a figure ? 48. ? secondary ? clk ? to ? output ? delay description device ? speed unit -1 -2 -3 min max min max min max primary ? clock ? skew ? information ? (pos ? edge ? to ? pos ? edge ? or ? neg ? edge ? to ? neg ? edge) or4e02 or4e04 or4e06 ? ? ? 85 110 120 ? ? ? 75 95 105 ? ? ? 70 90 100 ps ps ps primary ? clock ? skew ? information ? (pos ? edge ? to ? pos ? edge, ? neg ? edge ? to ? neg ? edge, ? pos ? edge ? to ? neg ? edge ? or ? neg ? edge ? to ? pos ? edge) or4e02 or4e04 or4e06 ? ? ? 265 285 300 ? ? ? 190 210 220 ? ? ? 180 200 210 ps ps ps description device ? speed unit -1 -2 -3 min max min max min max sclk ? output ? pin ? (lvttl-12 ? ma ? fast, ? output ? within ? 6 ? pics ? of ? sclk ? input) all ? 7.22 ? 6.70 ? 6.06 ns additional ? delay ? per ? each ? extra ? 6 ? pics ? per ? clock ? route ? direction. all ? 0.36 ? 0.38 ? 0.34 ns output ? (30 ? pf ? load) q d sclk pio ? ff
lattice semiconductor 87 data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) ? t able ? 51. ? primary ? clk ? (pclk) ? to ? output ? delay ? without ? on-chip ? plls ? (pin-to-pin) ? or4exx commercial: vdd15 = 1.425 v to 1.575 v, vdd33 = 3.0 v to 3.6 v, vddio = 3.0 v to 3.6 v, ?40 c < tj < +85 c; cl = 30 p. or4exx industrial: vdd15 = 1.425 v to 1.575 v, vdd33 = 3.0 v to 3.6 v, vddio = 3.0 v to 3.6 v, ?40 c < tj < +100 c; cl = 30 p. notes: ? 1. timing ? is ? without ? the ? use ? of ? the ? phase-locked ? loops ? (plls). 2. this ? clock ? delay ? is ? for ? a ? fully ? routed ? clock ? tree ? that ? uses ? the ? primary ? clock ? network. ? it ? includes ? both ? the ? l vttl ? (3.3 ? v) ? input ? clock ? buffer ? delay, ? the ? clock ? routing ? to ? the ? pio ? clk ? input, ? the ? clock q ? of ? the ? ff, ? and ? the ? delay ? through ? the ? l vttl ? (3.3 ? v) ? data ? output ? buffer. ? the ? pclk ? input ? clock ? is ? connected ? at ? the ? semi-dedicated ? primary ? clock ? input ? pins. 3. for ? timing ? improvements ? using ? other ? i/o ? buffer ? types ? for ? the ? input ? clock ? buffer ? or ? output ? data ? buffer, ? see ? t able ? 45 ? and ? t able ? 47. 5-4846(f).b figure 49. primary clock to output delay t able ? 52. ? primary ? clk ? (pclk) ? to ? output ? delay ? using ? on-chip ? plls ? (pin-to-pin) ? or4exx commercial: vdd15 = 1.425 v to 1.575 v, vdd33 = 3.0 v to 3.6 v, vddio = 3.0 v to 3.6 v, ?40 c < tj < +85 c; cl = 30 p. or4exx industrial: vdd15 = 1.425 v to 1.575 v, vdd33 = 3.0 v to 3.6 v, vddio = 3.0 v to 3.6 v, ?40 c < tj < +100 c; cl = 30 p. notes: ? 1. timing ? uses ? the ? automatic ? delay ? compensation ? mode ? of ? the ? plls. ? the ? feedback ? to ? the ? pll ? is ? provided ? by ? the ? global ? system ? clock ? routing. ? other ? delay ? values ? are ? possible ? by ? using ? the ? phase ? modifications ? mode ? of ? the ? pll ? instead. 2. this ? clock ? delay ? is ? for ? a ? fully ? routed ? clock ? tree ? that ? uses ? the ? primary ? clock ? network. ? it ? includes ? both ? the ? l vttl ? (3.3 ? v) ? input ? clock ? buffer ? delay, ? a ? pll ? block, ? the ? clock ? routing ? to ? the ? pio ? clk ? input, ? the ? clock q ? of ? the ? ff, ? and ? the ? delay ? through ? the ? l vttl ? (3.3 ? v) ? data ? output ? buffer. ? the ? pclk ? input ? clock ? is ? connected ? at ? the ? semi-dedicated ? pll ? input ? pin. 3. for ? timing ? improvements ? using ? other ? i/o ? buffer ? types ? for ? the ? input ? clock ? buffer ? or ? output ? data ? buffer, ? see ? t able ? 45 ? and ? t able ? 47. description device ? speed unit -1 -2 -3 min max min max min max pclk ? input ? pin ? output ? pin ? (lvttl-12 ? ma ? fast) or4e02 or4e04 or4e06 ? ? ? 9.00 9.24 9.42 ? ? ? 8.03 8.23 8.41 ? ? ? 7.28 7.46 7.62 ns ns ns description device ? speed unit -1 -2 -3 min max min max min max pclk ? input ? pin ? output ? pin ? (lvttl-12 ? ma ? fast) all ? 5.84 ? 5.27 ? 4.78 ns pll ? delay ? adjustments ? from ? cycle ? stealing ? (used ? to ? reduce ? clk->out ? by ? the ? min ? delay ? value ? shown): one ? delay ? cell two ? delay ? cells three ? delay ? cells pllcdel1 pllcdel2 pllcdel3 ? ? ? 0.89 1.64 2.43 ? ? ? 0.70 1.29 1.98 ? ? ? 0.64 1.18 1.80 ns ns ns output ? (30 ? pf ? load) q d pclk pio ? ff
88 lattice semiconductor data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) ? t able ? 53. ? secondary ? clk ? (sclk) ? setup/hold ? t ime ? without ? on-chip ? plls ? (pin-to-pin) or4exx commercial: vdd15 = 1.425 v to 1.575 v, vdd33 = 3.0 v to 3.6 v, vddio = 3.0 v to 3.6 v, ?40 c < tj < +85 c or4exx industrial: vdd15 = 1.425 v to 1.575 v, vdd33 = 3.0 v to 3.6 v, vddio = 3.0 v to 3.6 v, ?40 c < tj < +100 c notes: 1. the ? pin-to-pin ? timing ? parameters ? in ? this ? table ? will ? match ? isplever ? if ? the ? clock ? delay ? multiplier ? in ? the ? setup ? preference ? is ? set ? to ? 0.95 ? for ? setup ? time ? and ? 1.05 ? for ? hold ? time. 2. timing ? is ? without ? the ? use ? of ? the ? phase-locked ? loops ? (plls) ? or ? pio ? input ? ff ? cycle ? stealing ? delays ? (which ? can ? provide ? reductions ? in ? setup ? time ? at ? the ? expense ? of ? hold ? time). 3. this ? setup/hold ? time ? is ? for ? a ? fully ? routed ? clock ? tree ? that ? uses ? the ? secondary ? clock ? network. ? it ? includes ? both ? the ? l vttl ? (3.3 ? v) ? input ? clock ? buffer ? delay, ? the ? clock ? routing ? to ? the ? pio ? clk ? input, ? the ? setup/hold ? time ? of ? the ? pio ? ff ? (with ? the ? data ? input ? delay ? disabled) ? and ? the ? l vttl ? (3.3 ? v) ? input ? data ? buffer ? to ? pio ? ff ? delay. ? an ? sclk ? input ? clock ? can ? be ? at ? any ? input ? pin. 4. for ? timing ? improvements ? using ? other ? i/o ? buffer ? types ? for ? the ? input ? clock ? buffer ? or ? input ? data ? buffer, ? see ? t able ? 45. 5. the ? ort8850h ? fpsc ? has ? slightly ? reduced ? performance ? from ? the ? values ? in ? this ? table. ? isplever ? will ? report ? the ? actual ? delay ? values ? for ? all ? devices, ? including ? the ? ort8850h ? in ? this ? arrangement. ? 5-4847(f).b figure ? 50. ? input ? to ? secondary ? clk ? setup/hold ? t ime description device ? speed unit -1 -2 -3 min max min max min max input ? to ? sclk ? setup ? t ime ? (input ? within ? 6 ? pics ? of ? sclk ? input), ? fast ? capture ? enabled all 5.95 ? 5.54 ? 5.06 ? ns input ? to ? sclk ? setup ? t ime ? (input ? within ? 6 ? pics ? of ? sclk ? input), ? no ? input ? data ? delay all 0.00 ? ? 0.00 ? 0.00 ? ns reduced ? setup ? t ime ? per ? each ? extra ? 6 ? pics ? per ? clock ? route ? direction. all 0.36 ? 0.38 ? 0.34 ? ns input ? to ? sclk ? hold ? t ime ? (input ? within ? 6 ? pics ? of ? sclk ? input), ? fast ? capture ? enabled all 0.00 ? 0.00 ? 0.00 ? ns input ? to ? sclk ? hold ? t ime ? (input ? within ? 6 ? pics ? of ? sclk ? input), ? no ? input ? data ? delay all 3.07 ? 3.04 ? 2.74 ? ns additional ? hold ? t ime ? per ? each ? extra ? 6 ? pics ? per ? clock ? route ? direction. all 0.36 ? 0.38 ? 0.34 ? ns input ? delay ? adjustments ? from ? pio ? cycle ? stealing ? (typically ? used ? to ? reduce ? setup ? time ? by ? the ? min ? value ? shown): one ? delay ? cell two ? delay ? cells three ? delay ? cells icycdel1 icycdel2 icycdel3 ? ? ? 0.89 1.64 2.43 ? ? ? 0.70 1.29 1.98 ? ? ? 0.64 1.18 1.80 ns ns ns q d sclk input pio ? ff
lattice semiconductor 89 data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) ? t able ? 54. ? edge ? clk ? (eclk) ? setup/hold ? t ime ? without ? on-chip ? plls ? (pin-to-pin) or4exx commercial: v dd 15 = 1.425 v to 1.575 v, v dd 33 = 3.0 v to 3.6 v, v dd io = 3.0 v to 3.6 v, ?40 c < t j < +85 c or4exx industrial: v dd 15 = 1.425 v to 1.575 v, v dd 33 = 3.0 v to 3.6 v, v dd io = 3.0 v to 3.6 v, ?40 c < t j < +100 c notes: 1. the ? pin-to-pin ? timing ? parameters ? in ? this ? table ? will ? match ? isplever ? if ? the ? clock ? delay ? multiplier ? in ? the ? setup ? preference ? is ? set ? to ? 0.95 ? for ? setup ? time ? and ? 1.05 ? for ? hold ? time. 2. timing ? is ? without ? the ? use ? of ? the ? phase-locked ? loops ? (plls) ? or ? pio ? input ? ff ? cycle ? stealing ? delays ? (which ? can ? provide ? reductions ? in ? setup ? time ? at ? the ? expense ? of ? hold ? time). 3. this ? setup/hold ? time ? is ? for ? a ? fully ? routed ? clock ? tree ? that ? uses ? the ? edge ? clock ? network. ? it ? includes ? both ? the ? l vttl ? (3.3 ? v) ? input ? clock ? buffer ? delay, ? the ? clock ? routing ? to ? the ? pio ? clk ? input, ? the ? setup/hold ? time ? of ? the ? pio ? ff ? (with ? the ? data ? input ? delay ? disabled) ? and ? the ? l vttl ? (3.3 ? v) ? input ? data ? buffer ? to ? pio ? ff ? delay. ? edge ? clocks ? can ? only ? be ? connected ? to ? one ? pin ? or ? pin-pair ? per ? pic, ? those ? ending ? in ? the ? letter ? c ? for ? singled- ended ? and ? those ? ending ? in ? c ? and ? d ? for ? differential ? inputs. ? see ? the ? pinout ? section ? for ? more ? details. 4. for ? timing ? improvements ? using ? other ? i/o ? buffer ? types ? for ? the ? input ? clock ? buffer ? or ? input ? data ? buffer, ? see ? t able ? 45. 5. the ? ort8850h ? fpsc ? has ? slightly ? reduced ? performance ? from ? the ? values ? in ? this ? table. ? isplever ? will ? report ? the ? actual ? delay ? values ? for ? all ? devices, ? including ? the ? ort8850h ? in ? this ? arrangement. ? 5-4847(f).b figure ? 51. ? input ? to ? edge ? clk ? setup/hold ? t ime description device ? speed unit -1 -2 -3 min max min max min max input to eclk setup time (input within 6 pics of eclk input), fast capture enabled all 1.13 ? 1.17 ? 1.08 ? ns input to eclk setup time (input within 6 pics of eclk input), fast input enabled all 0.00 ? 0.00 ? 0.00 ? ns reduced setup time per each extra 6 pics per clock route direction. all 0.36 ? 0.38 ? 0.34 ? ns input to eclk hold time (input within 6 pics of eclk input), fast capture enabled all 0.00 ? 0.00 ? 0.00 ? ns input to eclk hold time (input within 6 pics of eclk input), fast input enabled all 2.68 ? 2.65 ? 2.40 ? ns additional hold time per each extra 6 pics per clock route direction. all 0.36 ? 0.38 ? 0.34 ? ns input delay adjustments from pio cycle stealing (typically used to reduce setup time by the min value shown): one delay cell tw o delay cells three delay cells icycdel1 icycdel2 icycdel3 ? ? ? 0.89 1.64 2.43 ? ? ? 0.70 1.29 1.98 ? ? ? 0.64 1.18 1.80 ns ns ns q d eclk input pio ? ff
90 lattice semiconductor data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) ? t able ? 55. ? primary ? clk ? (pclk) ? setup/hold ? t ime ? without ? on-chip ? plls ? (pin-to-pin) or4exx commercial: v dd 15 = 1.425 v to 1.575 v, v dd 33 = 3.0 v to 3.6 v, v dd io = 3.0 v to 3.6 v, ?40 c < t j < +85 c or4exx industrial: v dd 15 = 1.425 v to 1.575 v, v dd 33 = 3.0 v to 3.6 v, v dd io = 3.0 v to 3.6 v, ?40 c < t j < +100 c notes: ? 1. the ? pin-to-pin ? timing ? parameters ? in ? this ? table ? will ? match ? isplever ? if ? the ? clock ? delay ? multiplier ? in ? the ? setup ? preference ? is ? set ? to ? 0.95 ? for ? setup ? time ? and ? 1.05 ? for ? hold ? time. 2. timing ? is ? without ? the ? use ? of ? the ? phase-locked ? loops ? (plls) ? or ? pio ? input ? ff ? cycle ? stealing ? delays ? (which ? can ? provide ? reductions ? in ? setup ? time ? at ? the ? expense ? of ? hold ? time). 3. this ? setup/hold ? time ? is ? for ? a ? fully ? routed ? clock ? tree ? that ? uses ? the ? primary ? clock ? network. ? it ? includes ? both ? the ? l vttl ? (3.3 ? v) ? input ? clock ? buffer ? delay, ? the ? clock ? routing ? to ? the ? pio ? clk ? input, ? the ? setup/hold ? time ? of ? the ? pio ? ff ? (with ? the ? data ? input ? delay ? disabled) ? and ? the ? l vttl ? (3.3 ? v) ? input ? data ? buffer ? to ? pio ? ff ? delay. ? the ? pclk ? input ? clock ? is ? connected ? at ? the ? semi-dedicated ? primary ? clock ? input ? pins. 4. for ? timing ? improvements ? using ? other ? i/o ? buffer ? types ? for ? the ? input ? clock ? buffer ? or ? input ? data ? buffer, ? see ? t able ? 45. 5-4847(f).a figure ? 52. ? input ? to ? primary ? clock ? setup/hold ? t ime description device ? speed unit -1 -2 -3 min max min max min max input to pclk setup time, input data delay enabled or4e02 or4e04 or4e06 4.37 4.19 4.06 ? ? ? 4.36 4.21 4.09 ? ? ? 3.99 3.85 3.75 ? ? ? ns ns ns input to pclk setup time, no input data delay or4e02 or4e04 or4e06 0.00 0.00 0.00 ? ? ? 0.00 0.00 0.00 ? ? ? 0.00 0.00 0.00 ? ? ? ns ns ns input to pclk hold time, input data delay enabled or4e02 or4e04 or4e06 0.00 0.00 0.00 ? ? ? 0.00 0.00 0.00 ? ? ? 0.00 0.00 0.00 ? ? ? ns ns ns input to pclk hold time, no input data delay or4e02 or4e04 or4e06 4.93 5.17 5.38 ? ? ? 4.45 4.66 4.84 ? ? ? 4.02 4.21 4.37 ? ? ? ns ns ns input delay adjustments from pio cycle stealing (typically used to reduce setup time by the min value shown): one delay cell tw o delay cells three delay cells icycdel1 icycdel2 icycdel3 ? ? ? 0.89 1.64 2.43 ? ? ? 0.70 1.29 1.98 ? ? ? 0.64 1.18 1.80 ns ns ns q d pclk input pio ? ff
lattice semiconductor 91 data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) t able ? 56. ? primary ? clk ? (pclk) ? setup/hold ? t ime ? using ? on-chip ? plls ? (pin-to-pin) or4exx commercial: vdd15 = 1.425 v to 1.575 v, vdd33 = 3.0 v to 3.6 v, vddio = 3.0 v to 3.6 v, ?40 c < tj < +85 c or4exx industrial: vdd15 = 1.425 v to 1.575 v, vdd33 = 3.0 v to 3.6 v, vddio = 3.0 v to 3.6 v, ?40 c < tj < +100 c notes: ? 1. the ? pin-to-pin ? timing ? parameters ? in ? this ? table ? will ? match ? isplever ? if ? the ? clock ? delay ? multiplier ? in ? the ? setup ? preference ? is ? set ? to ? 0.95 ? for ? setup ? time ? and ? 1.05 ? for ? hold ? time. 2. timing ? uses ? the ? automatic ? delay ? compensation ? mode ? of ? the ? plls. ? the ? feedback ? to ? the ? pll ? is ? provided ? by ? the ? global ? system ? clock ? routing. ? other ? delay ? values ? are ? possible ? by ? using ? the ? phase ? modifications ? mode ? of ? the ? pll ? instead. 3. this ? setup/hold ? time ? is ? for ? a ? fully ? routed ? clock ? tree ? that ? uses ? the ? primary ? clock ? network. ? it ? includes ? both ? the ? l vttl ? (3.3 ? v) ? input ? clock ? buffer ? delay, ? pll ? block, ? the ? clock ? routing ? to ? the ? pio ? clk ? input, ? the ? setup/hold ? time ? of ? the ? pio ? ff ? (with ? the ? data ? input ? delay ? disabled) ? and ? the ? l vttl ? (3.3 ? v) ? input ? data ? buffer ? to ? pio ? ff ? delay. ? the ? pclk ? input ? clock ? is ? connected ? at ? the ? semi-dedicated ? pll ? input ? pin. 4. note ? that ? the ? pio ? cycle ? stealing ? delay ? adjustments ? and ? the ? pll ? cycle ? stealing ? delay ? adjustments ? are ? each ? attempting ? to ? pull ? the ? same ? clock ? in ? both ? directions. ? if ? both ? are ? being ? used, ? then ? the ? difference ? between ? them ? will ? provide ? the ? basis ? for ? pio ? setup ? and ? hold ? times. 5. for ? timing ? improvements ? using ? other ? i/o ? buffer ? types ? for ? the ? input ? clock ? buffer ? or ? input ? data ? buffer, ? see ? t able ? 45. description device ? speed unit -1 -2 -3 min max min max min max input to pclk setup time, input data delay enabled all 7.73 ? 7.30 ? 6.66 ? ns input to pclk setup time, no input data delay all 0.00 ? 0.00 ? 0.00 ? ns input to pclk hold time, input data delay enabled all 0.00 ? 0.00 ? 0.00 ? ns input to pclk hold time, no input data delay all 1.82 ? 1.73 ? 1.57 ? ns input delay adjustments from pio cycle stealing (typically used to reduce setup time by the min value shown): one delay cell tw o delay cells three delay cells icycdel1 icycdel2 icycdel3 ? ? ? 0.89 1.64 2.43 ? ? ? 0.70 1.29 1.98 ? ? ? 0.64 1.18 1.80 ns ns ns pll delay adjustments from cycle stealing (used to reduce hold by the min delay value shown): one delay cell tw o delay cells three delay cells pllcdel1 pllcdel2 pllcdel3 ? ? ? 0.89 1.64 2.43 ? ? ? 0.70 1.29 1.98 ? ? ? 0.64 1.18 1.80 ns ns ns
92 lattice semiconductor data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) configuration ? t iming t able ? 57. ? general ? configuration ? mode ? t iming ? characteristics or4exx commercial/industrial: vdd15 = 1.4 v to 1.6 v, vdd33 = 3.0 v to 3.6 v, vddio = 3.0 v to 3.6 v, ?40 c < tj < +125 c;cl = 30 pf * not applicable to asynchronous peripheral mode. ?v alues are shown for the mpi in 32-bit mode with daisy-chaining through the dout pin disabled. p arameter symbol min max unit all con guration modes m[3:0] setup time to init high tsmode 0.00 ? ns m[3:0] hold time from init high thmode 600.00 ? ns reset pulse width low to start recon guration trw 50.00 ? ns prgm pulse width low to start recon guration tpgw 50.00 ? ns master and asynchronous peripheral modes po w er-on reset delay cclk period (m3 = 0) (m3 = 1) con guration latency (autoincrement mode, no ebr initialization): or4e02 (m3 = 0) (m3 = 1) or4e04 (m3 = 0) (m3 = 1) or4e06 (m3 = 0) (m3 = 1) tpo tcclk tcl 15.70 60.00 480.00 69.7 557.6 187.7 1,501.5 284.2 2,273.9 52.40 200.00 1,600.00 232.3 1,858.6 625.6 5,004.9 947.5 7,579.7 ms ns ns ms ms ms ms ms ms microprocessor ( mpi ) mode ? po w er-on reset delay mpi clock period con guration latency (autoincrement mode, no ebr initialization): or4e02 or4e04 or4e06 tpo tcl 15.70 15.00 290,412 782,018 1,184,322 52.40 ? ? ? ? ms mpi clk cycles mpi clk cycles mpi clk cycles pa r tial recon guration (per data frame): or4e02 or4e04 or4e06 tpr 225 321 385 ? ? ? mpi clk cycles mpi clk cycles mpi clk cycles slave serial mode po w er-on reset delay cclk period con guration latency (autoincrement mode, no ebr initialization): or4e02 or4e04 or4e06 tpo tcclk tcl 3.90 10.00 11.6 31.3 47.4 13.10 ? ? ? ? ms ns ms ms ms pa r tial recon guration (per data frame): or4e02 or4e04 or4e06 tpr 9.0 12.8 15.4 ? ? ? s s s
lattice semiconductor 93 data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) ta b le 58. general con guration mode timing characteristics (continued) or4exx commercial/industrial: vdd15 = 1.4 v to 1.6 v, vdd33 = 3.0 v to 3.6 v, vddio = 3.0 v to 3.6 v, ?40 c < tj < +125 c;cl = 30 pf . note: ? t po ? is ? triggered ? when ? v dd 33 ? reaches ? between ? 2.7 ? v ? and ? 3.0 ? v. parameter symbol min max unit slave parallel mode po w er-on reset delay cclk period: con guration latency (normal mode): or4e02 or4e04 or4e06 tpo tcclk tcl 3.90 10.00 1.5 3.9 5.9 13.10 ? ? ? ? ms ns ms ms ms pa r tial recon guration (per data frame): or4e02 or4e04 or4e06 tpr 1.1 1.6 1.9 ? ? ? s s s init timing init high to cclk delay: slave parallel slave serial master serial master parallel tinit_cclk 0.50 0.50 0.50 0.50 1.60 1.60 1.60 1.60 s s s s initialization latency (prgm high to init high): or4e02 or4e04 or4e06 til 0.43 0.58 0.74 1.44 1.95 2.46 ms ms ms init high to wr , asynchronous peripheral tinit_wr 2.00 ? s
94 lattice semiconductor data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) 5-4531(f).a figure ? 53. ? general ? configuration ? mode ? t iming ? diagram v dd 15, v dd 33 cclk m[3:0] prgm init t po + t il t il t cclk t smode t hmode t init_clk done t cl t pgw
lattice semiconductor 95 data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) ? t able ? 59. ? master ? serial ? configuration ? mode ? t iming ? characteristics or4exx ? commercial/industrial: ? vdd15 ? = ? 1.4 ? v ? to ? 1.6 ? v, ? vdd33 ? = ? 3.0 ? v ? to ? 3.6 ? v, ? vddio ? = ? 3.0 ? v ? to ? 3.6 ? v, ? ?40 ? c ? < ? tj ? < ? +125 ? c; ? cl ? = ? 30 ? pf. note: ? serial ? configuration ? data ? is ? transmitted ? out ? on ? dout ? on ? the ? rising ? edge ? of ? cclk ? after ? it ? is ? input ? on ? din. * data ? gets ? clocked ? out ? from ? an ? external ? serial ? rom. ? the ? clock ? to ? data ? delay ? of ? the ? serial ? rom ? must ? be ? less ? than ? the ? cclk ? frequency ? since ? the ? data ? available ? out ? of ? the ? serial ? rom ? must ? be ? setup ? and ? waiting ? to ? be ? clocked ? into ? the ? fpga ? before ? the ? next ? cclk ? rising ? edge. 5-4532(f).b figure ? 54. ? master ? serial ? configuration ? mode ? t iming ? diagram parameter symbol min max unit din ? setup ? t ime* t s 10.00 ? ns din ? hold ? t ime t h 0.00 ? ns cclk ? frequency ? (m3 ? = ? 0) f c 5.00 16.67 mhz cclk ? frequency ? (m3 ? = ? 1) f c 0.63 2.08 mhz cclk ? to ? dout ? delay t d ? 5.00 ns din cclk dout t s t h bit n bit n t d
96 lattice semiconductor data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) ? t able ? 60. ? master ? parallel ? configuration ? mode ? t iming ? characteristics or4exx ? commercial/industrial: ? vdd15 ? = ? 1.4 ? v ? to ? 1.6 ? v, ? vdd33 ? = ? 3.0 ? v ? to ? 3.6 ? v, ? vddio ? = ? 3.0 ? v ? to ? 3.6 ? v, ? ?40 ? c ? < ? tj ? < ? +125 ? c; ? cl ? = ? 30 ? pf . ? note: the ? rclk ? period ? consists ? of ? seven ? cclks ? for ? rclk ? low ? and ? one ? cclk ? for ? rclk ? high. serial ? data ? is ? transmitted ? out ? on ? dout ? two ? cclk ? cycles ? after ? the ? byte ? is ? input ? on ? d[7:0]. ? 2706(f) figure ? 55. ? master ? parallel ? configuration ? mode ? t iming ? diagram parameter symbol min max unit rclk ? to ? address ? v alid t av ? 10.00 ns d[7:0] ? setup ? t ime ? to ? rclk ? high t s 10.00 ? ns d[7:0] ? hold ? t ime ? to ? rclk ? high t h 0.00 ? ns rclk ? low ? t ime t cl 7.00 7.00 cclk ? cycles rclk ? high ? t ime t ch 1.00 1.00 cclk ? cycles cclk ? to ? dout t d ? 5.00 ns a[21:0] rclk d[7:0] t cl t ch t av cclk dout t h t s byte ? n byte ? n ? + ? 1 d0 d1 d2 d3 d4 d5 d6 d7 t d
lattice semiconductor 97 data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) t able ? 61. ? asynchronous ? peripheral ? configuration ? mode ? t iming ? characteristics or4exx ? commercial/industrial: ? vdd15 ? = ? 1.4 ? v ? to ? 1.6 ? v, ? vdd33 ? = ? 3.0 ? v ? to ? 3.6 ? v, ? vddio ? = ? 3.0 ? v ? to ? 3.6 ? v, ? ?40 ? c ? < ? tj ? < ? +125 ? c; ? cl ? = ? 30 ? pf . * the ? smaller ? delay ? is ? for ? fast ? asynchronous ? peripheral ? mode ? (mode ? pins ? m[3:0]=?0101?) ? and ? the ? larger ? delay ? is ? for ? slow ? asynchronous ? periph- eral ? mode ? (mode ? pins ? m[3:0]=?1101?). ? this ? parameter ? is ? valid ? whether ? the ? end ? of ? not ? rdy ? is ? determined ? from ? the ? rdy ? pin ? or ? from ? the ? d7 ? pin. note: serial ? data ? is ? transmitted ? out ? on ? dout ? on ? the ? rising ? edge ? of ? cclk ? after ? the ? byte ? is ? input ? on ? d[7:0]. ? d[2:0] ? timing ? is ? the ? same ? as ? the ? write ? data ? portion ? of ? the ? d[7:3] ? waveform ? because ? d[2:0] ? are ? not ? enabled ? by ? rd . 5-4533(f).b figure ? 56. ? asynchronous ? peripheral ? configuration ? mode ? t iming ? diagram parameter symbol min max unit wr , ? cs0 , ? and ? cs1 ? pulse ? width twr 10.00 60.00 ? / ? 500.00* ns d[7:0] ? setup ? t ime: ts 0.00 ? ns rdy ? delay trdy ? 10.00 ns rdy ? low tb 1.00 8.00 cclk ? periods earliest ? wr ? after ? rdy ? goes ? high? twr2 0.00 ? ns rd ? to ? d[7:0] ? enable/disable tden ? 10.00 ns cclk ? to ? dout td ? 5.00 ns cs1 d[7:3] cclk dout cs0 rdy d0 d1 d2 t b t wr t s t rdy wr d7 t d previous ? byte t wr2 write ? data d3 t den t den rd
98 lattice semiconductor data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) t able ? 62. ? slave ? serial ? configuration ? mode ? t iming ? characteristics or4exx ? commercial/industrial: ? vdd15 ? = ? 1.4 ? v ? to ? 1.6 ? v, ? vdd33 ? = ? 3.0 ? v ? to ? 3.6 ? v, ? vddio ? = ? 3.0 ? v ? to ? 3.6 ? v, ? ?40 ? c ? < ? tj ? < ? +125 ? c; ? cl ? = ? 30 ? pf. ? note: ? serial ? configuration ? data ? is ? transmitted ? out ? on ? dout ? on ? the ? rising ? edge ? of ? cclk ? after ? it ? is ? input ? on ? din. ? 5-4535(f).b figure ? 57. ? slave ? serial ? configuration ? mode ? t iming ? diagram ? parameter symbol min max unit din ? setup ? t ime t s 5.00 ? ns din ? hold ? t ime t h 0.00 ? ns cclk ? high ? t ime t ch 5.00 ? ns cclk ? low ? t ime t cl 5.00 ? ns cclk ? frequency f c ? 100.00 mhz cclk ? to ? dout t d ? 5.00 ns din cclk dout t d t s t h t cl t ch bit n bit n
lattice semiconductor 99 data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) ? t able ? 63. ? slave ? parallel ? configuration ? mode ? t iming ? characteristics or4exx ? commercial/industrial: ? vdd15 ? = ? 1.4 ? v ? to ? 1.6 ? v, ? vdd33 ? = ? 3.0 ? v ? to ? 3.6 ? v, ? vddio ? = ? 3.0 ? v ? to ? 3.6 ? v, ? ?40 ? c ? < ? tj ? < ? +125 ? c; ? cl ? = ? 30 ? pf. ? note: ? daisy-chaining ? of ? fpgas ? is ? not ? supported ? in ? this ? mode. ? 5-2848(f) figure ? 58. ? slave ? parallel ? configuration ? mode ? t iming ? diagram ? parameter symbol min max unit cs0 , ? cs1, ? wr ? setup ? t ime ts1 5.00 ? ns cs0 , ? cs1, ? wr ? hold ? t ime th1 2.00 ? ns d[7:0] ? setup ? t ime ts2 5.00 ? ns d[7:0] ? hold ? t ime th2 0.00 ? ns cclk ? high ? t ime tch 5.00 ? ns cclk ? low ? t ime tcl 5.00 ? ns cclk ? frequency fc ? 100.00 mhz t s1 t s2 t h2 cs1 cclk d[7:0] cs0 wr t cl t ch t h1
100 lattice semiconductor data sheet november, 2002 orca series 4 fpgas t iming ? characteristics ? (continued) readback ? t iming ? t able ? 64 . ? readback ? t iming ? characteristics or4exx ? commercial/industrial: ? vdd15 ? = ? 1.4 ? v ? to ? 1.6 ? v, ? vdd33 ? = ? 3.0 ? v ? to ? 3.6 ? v, ? vddio ? = ? 3.0 ? v ? to ? 3.6 ? v, ? ?40 ? c ? < ? tj ? < ? +125 ? c; ? cl ? = ? 30 ? pf. 5-4536(f) figure ? 59. ? readback ? t iming ? diagram parameter symbol min max unit rd_cfg ? to ? cclk ? setup ? t ime t s 5.00 ? ns rd_cfg ? high ? width ? to ? abort ? readback t rba 2? cclk ? cycles cclk ? low ? t ime t cl 5.00 ? ns cclk ? high ? t ime t ch 5.00 ? ns cclk ? frequency f c ? 100.00 mhz cclk ? to ? rd_data ? delay t d ? 5.00 ns t d t ch cclk rd_data t s t cl rd_cfg bit ? 0 bit ? 1 bit ? 0 t rba
lattice semiconductor 101 data sheet november, 2002 orca series 4 fpgas pin information pin descriptions this section describes the pins found on the series 4 fpgas. any pin not described in this table is a user-program- mable i/o. during con guration, the user-programmable i/os are 3-stated with an internal pull-up resistor enabled. if any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled after con guration. the pin descriptions in table 65 and throughout this data sheet show active-low signals with an ov erscore. the package pinout tables that follow, show this as a signal ending with _n, for ldc and ldc_n are equivalent. ta b le 65. pin descriptions symbol i/o description dedicated pins v dd 33 ? 3.3 v positive power supply. this power supply is used for 3.3 v con guration rams and internal plls. when using plls, this power supply should be well isolated from all other power supplies on the board for proper operation. v dd 15 ? 1.5 v positive power supply for internal logic. v dd io ? positive power supply used by i/o banks. v ss ? ground. ptemp i temperature sensing diode pin. dedicated input. reset i during con guration, reset forces the restart of con guration and a pull-up is enabled. after con guration, reset can be used as a general fpga input or as a direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk o in the master and asynchronous peripheral modes, cclk is an output which strobes con- guration data in. i in the slave or readback after con guration, cclk is input synchronous with the data on din or d[7:0]. cclk is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. done i as an input, a low level on done delays fpga start-up after con guration.* o as an active-high, open-drain output, a high level on this signal indicates that con gura- tion is complete. done has an optional pull-up resistor. prgm i prgm is an active-low input that forces the restart of con guration and resets the bound- ary-scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the init pin goes high. this pin always has an active pull-up. during con guration, rd_cfg is an active-low input that activates the ts_all function and 3-states all of the i/o. after con guration, rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the con guration data, including pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides con gura- tion data out. if used in boundary-scan, tdo is test data out. cfg_irq /mpi_irq o during jtag, slave, master, and asynchronous peripheral con guration assertion on this cfg_irq (active-low) indicates an error or errors for block ram or fpsc initialization. mpi active-low interrupt request output, when the mpi is used. * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con guration pins (and the activation of all user i/os) is controlled by a second set of options.
102 lattice semiconductor data sheet november, 2002 orca series 4 fpgas pin information (continued) ta b le 65. pin descriptions (continued) symbol i/o description special-purpose pins m[3:0] i during powerup and initialization, m0?m3 are used to select the con guration mode with their values latched on the rising edge of init . during con guration, a pull-up is enabled. i/o after con guration, these pins are user-programmable i/o.* pll_ck[0:7][tc] i semi-dedicated pll clock pins. during con guration they are 3-stated with a pull up. i/o these pins are user-programmable i/o pins if not used by plls after con guration. p[tblr]clk[1:0][tc] i pins dedicated for the primary clock. input pins on the middle of each side with differential pairing. i/o after con guration these pins are user programmable i/o, if not used for clock inputs. tdi, tck, tms i if boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary-scan is not selected, all boundary-scan functions are inhibited once con guration is complete. even if boundary-scan is not used, either tck or tms must be held at logic 1 during con guration. each pin has a pull-up enabled during con guration. i/o after con guration, these pins are user-programmable i/o in boundary scan is not used.* rdy/b usy /rclk o during con guration in asynchronous peripheral mode, rdy/rclk indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same status is also available on d7 in asynchronous peripheral mode. during the master parallel con guration mode, rclk is a read output signal to an exter- nal memory. this output is not normally used. i/o after con guration this pin is a user-programmable i/o pin.* hdc o high during con guration is output high until con guration is complete. it is used as a con- trol output, indicating that con guration is not complete. i/o after con guration, this pin is a user-programmable i/o pin.* ldc o lo w dur ing con gur ation is output low until con guration is complete. it is used as a control output, indicating that con guration is not complete. i/o after con guration, this pin is a user-programmable i/o pin.* init i/o init is a bidirectional signal before and during con guration. during con guration, a pull- up is enabled, but an external pull-up resistor is recommended. as an active-low open- drain output, init is held low during power stabilization and internal clearing of memory. as an active-low input, init holds the fpga in the wait-state before the start of con gura- tion. after con guration, this pin is a user-programmable i/o pin.* cs0 , cs1 i cs0 and cs1 are used in the asynchronous peripheral, slave parallel, and microprocessor con guration modes. the fpga is selected when cs0 is low and cs1 is high. during con- guration, a pull-up is enabled. i/o after con guration, if mpi is not used, these pins are user-programmable i/o pins.* rd /mpi_strb i rd is used in the asynchronous peripheral con guration mode. a low on rd changes d[7:3] into a status output. w r and rd should not be used simultaneously. if they are, the write strobe overrides. this pin is also used as the mpi data transfer strobe. as a status indication, a high indicates ready, and a low indicates busy. i/o after con guration, if the mpi is not used, this pin is a user-programmable i/o pin.* * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con guration pins (and the activation of all user i/os) is controlled by a second set of options.
lattice semiconductor 103 data sheet november, 2002 orca series 4 fpgas pin information (continued) ta b le 65. pin descriptions (continued) symbol i/o description special-purpose pins (continued) wr /mpi_rw i wr is used in asynchronous peripheral mode. a low on wr transfers data on d[7:0] to the fpga. in mpi mode, a high on mpi_rw allows a read from the data bus, while a low causes a write transfer to the fpga. i/o after con guration, if the mpi is not used, wr /mpi_rw is a user-programmable i/o pin.* ppc_a[14:31] i during mpi mode the ppc_a[14:31] are used as the address bus driven by the po w erpc b us master utilizing the least-signi cant bits of the po w erpc 32-bit address. mpi_b urst im pi_b urst is driven low to indicate a burst transfer is in progress in mpi mode. driven high indicates that the current transfer is not a burst. mpi_bdip im pi_bdip is driven by the po w erpc processor in mpi mode. assertion of this pin indicates that the second beat in front of the current one is requested by the master. negated before the burst transfer ends to abort the burst data phase. mpi_tsz[0:1] i mpi_tsz[0:1] signals are driven by the bus master in mpi mode to indicate the data transfer size for the transaction. set 01 for byte, 10 for half-word, and 00 for word. a[21:0] o during master parallel mode a[21:0] address the con guration eproms up to 4m bytes. i/o if not used for mpi these pins are user-programmable i/o pins after con guration.* mpi_a ck o in mpi mode this is driven low indicating the mpi received the data on the write cycle or returned data on a read cycle. i/o if not used for mpi these pins are user-programmable i/o pins after con guration.* mpi_clk i this is the po w erpc synchronous, positive-edge bus clock used for the mpi interface. it can be a source of the clock for the embedded system bus. if mpi is used this will be the amba b us clock. i/o if not used for mpi these pins are user-programmable i/o pins after con guration.* mpi_tea oa low on the mpi transfer error acknowledge indicates that the mpi detects a bus error on the internal system bus for the current transaction. i/o if not used for mpi these pins are user-programmable i/o pins after con guration.* mpi_r tr y o this pin requests the mpc860 to relinquish the bus and retry the cycle. i/o if not used for mpi these pins are user-programmable i/o pins after con guration.* d[0:31] i/o selectable data bus width from 8, 16, 32-bit in mpi mode. driven by the bus master in a write transaction and driven by mpi in a read transaction. i d[7:0] receive con guration data during master parallel, peripheral, and slave parallel con g- uration modes when wr is low and each pin has a pull-up enabled. during serial con gura- tion modes, d0 is the din input. o d[7:3] output internal status for asynchronous peripheral mode when rd is low. i/o after con guration, if mpi is not used, the pins are user-programmable i/o pins.* dp[0:3] i/o selectable parity bus width in mpi mode from 1, 2, 4-bit, dp[0] for d[0:7], dp[1] for d[8:15], dp[2] for d[16:23], and dp[3] for d[24:31]. after con guration, if mpi is not used, the pins are user-programmable i/o pin.* * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con guration pins (and the activation of all user i/os) is controlled by a second set of options.
104 lattice semiconductor data sheet november, 2002 orca series 4 fpgas pin information (continued) ta b le 65. pin descriptions (continued) symbol i/o description special-purpose pins (continued) din i during slave serial or master serial con guration modes, din accepts serial con guration data synchronous with cclk. during parallel con guration modes, din is the d0 input. dur- ing con guration, a pull-up is enabled. i/o after con guration, this pin is a user-programmable i/o pin.* dout o during con guration, dout is the serial data output that can drive the din of daisy-chained slave devices. data out on dout changes on the rising edge of cclk. i/o after con guration, dout is a user-programmable i/o pin.* testcfg i during con guration this pin should be held high, to allow con guration to occur. a pull up is enabled during con guration. i/o after con guration, testcfg is a user programmable i/o pin.* * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con guration pins (and the activation of all user i/os) is controlled by a second set of options.
lattice semiconductor 105 data sheet november, 2002 orca series 4 fpgas pin information (continued) pa ck ag e compatibility ta b le 66 provides the number of user i/os available for the orca series 4 fpgas for each available package. each package has six dedicated con guration pins. t able ? 67 ? thru ? t able ? 69 ? provide ? the ? package ? pin ? and ? pin ? function ? for ? the ? series ? 4 ? fpgas ? and ? packages. ? the ? bond ? pad ? name ? is ? identified ? in ? the ? pio ? nomeclature ? used ? in ? the ? isplever ? design ? editor. ? the ? bank ? column ? provides ? information ? as ? to ? which ? output ? voltage ? level ? bank ? the ? given ? pin ? is ? in. ? the ? group ? column ? provides ? information ? as ? to ? the ? group ? of ? pins ? the ? given ? pin ? is ? in. ? this ? is ? used ? to ? show ? which ? vref ? pin ? is ? used ? to ? provide ? the ? reference ? voltage ? for ? single-ended ? limited-swing ? i/os. ? if ? none ? of ? these ? buffer ? types ? (such ? as ? sstl, ? gtl, ? hstl) ? are ? used ? in ? a ? given ? group, ? then ? the ? vref ? pin ? is ? available ? as ? an ? i/o ? pin. when ? the ? number ? of ? fpga ? bond ? pads ? exceeds ? the ? number ? of ? package ? pins, ? bond ? pads ? are ? unused. ? when ? the ? number ? of ? package ? pins ? exceeds ? the ? number ? of ? bond ? pads, ? package ? pins ? are ? left ? unconnected ? (no ? connects). ? when ? a ? package ? pin ? is ? to ? be ? left ? as ? a ? no ? connect ? for ? a ? specific ? die, ? it ? is ? indicated ? as ? a ? note ? in ? the ? device ? column ? for ? the ? fpga. ? the ? tables ? provide ? no ? information ? on ? unused ? pads. in ? order ? to ? allow ? pin-for-pin ? compatible ? board ? layouts ? that ? can ? accommodate ? both ? devices, ? some ? key ? compatibility ? issues ? include ? the ? following.: shared ? control ? signals ? on ? i/o ? registers. ? the ? orca ? series ? 4 ? architecture ? shares ? clock ? and ? control ? signals ? between ? two ? adjacent ? i/o ? pads. ? if ? i/o ? registers ? are ? used, ? incompatibilities ? may ? arise ? between ? devices ? when ? dif- ferent ? clock ? or ? control ? signals ? are ? needed ? on ? adjacent ? package ? pins. ? this ? is ? because ? one ? device ? may ? allow ? inde- pendent ? clock ? or ? control ? signals ? on ? these ? adjacent ? pins, ? while ? the ? other ? may ? force ? them ? to ? be ? the ? same. ? there ? are ? two ? ways ? to ? avoid ? this ? issue. ? ? always ? keep ? an ? open ? bonded ? pin ? (non-bonded ? pins ? do ? not ? count) ? between ? pins ? that ? require ? different ? clock ? or ? control ? signals. ? note ? that ? this ? open ? pin ? can ? be ? used ? to ? connect ? signals ? that ? do ? not ? require ? the ? use ? of ? i/o ? regis- ters ? to ? meet ? timing. ? ? place ? and ? route ? the ? design ? in ? all ? target ? devices ? to ? verify ? they ? produce ? valid ? designs. ? note ? that ? this ? method ? guarantees ? the ? current ? design, ? but ? does ? not ? necessarily ? guard ? against ? issues ? that ? can ? occur ? when ? design ? changes ? are ? made ? that ? affect ? i/o ? registers. ? ? 2x/4x ? i/o ? shift ? registers. ? if ? 2x ? i/o ? shift ? registers ? or ? 4x ? i/o ? shift ? registers ? are ? used ? in ? the ? design, ? this ? may ? cause ? incompatibilities ? between ? the ? devices ? because ? only ? the ? a ? and ? c ? i/os ? in ? a ? pic ? support ? 2x ? i/o ? shift ? regis- ters ? and ? only ? a ? i/os ? supports ? 4x ? i/o ? shift ? register ? mode. ? a ? and ? c ? i/os ? are ? shown ? in ? the ? following ? pinout ? tables ? under ? the ? i/o ? pad ? columns ? as ? those ? ending ? in ? a ? or ? c. edge clock input pins. the input buffers for fast edge clocks are only available at the c i/o pad. the c i/os are shown in the following pinout tables under the i/o pad columns as those ending in c. 680 pbgam differential i/o pairs. note that the or4e02 device in the 680 pbgam package has two less dif- f erential i/o pairs available than the or4e04 or or4e06, even though the total number of user i/os are the same f or all three devices.
106 lattice semiconductor data sheet november, 2002 orca series 4 fpgas pin information (continued) tab le 66. orca series 4 i/os summary note: each vref pin required reduces the available user i/os. as shown in the pair column, differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is the nineteenth pair in an associated bank). the c indicates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location of adjacent balls in either the horizontal or vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. v ref pins, shown in the additional function column, are associated to the bank and group (e.g., v ref _tl_01 is the v ref for group one of the top left (tl) bank). device 352 pbga 416 pbgam 680 pbgam or4e02/or4e04/or4e06 user i/o single ended 262 290 466 (4e4, 4e6) 405 (4e2) user i/o differential pairs (lvds, l vpecl) 128 139 197 (4e4, 4e6) 195 (4e2) con guration 7 7 7 dedicated function 3 3 3 v dd 15 16 28 48 v dd 33 8 8 8 v dd io 24 32 60 v ss 68 48 88 single-ended/differential i/o per bank bank 0 39/19 46/22 68/32 bank 1 26/13 28/14 47/20 bank 2 32/16 35/17 54/24 (23 for 4e2) bank 3 33/16 37/18 63/22 (21 for 4e2) bank 4 34/16 38/17 52/22 bank 5 24/12 24/12 44/18 bank 6 40/19 45/21 76/32 bank 7 34/17 37/18 62/27
lattice semiconductor 107 data sheet november, 2002 orca series 4 fpgas 352-pin pbga pinout ta b le 67. 352-pin pbga pinout b a352 v dd io bank v ref group i/o or4e02 or4e04 or4e06 additional function p air a1 ? ? vss vss vss vss ? ? b1 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? c2 ? ? o prd_da ta prd_dat a prd_dat a rd_data/tdo ? aa23 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? c1 ? ? i preset _n preset_ n preset_ n reset_n ? d2 ? ? i prd_cf g_n prd_cfg _n prd_cfg _n rd_cfg_n ? d3 ? ? i pprgr m_n pprgrm _n pprgrm _n prgrm_n ? d1 0 (tl) ? v dd io0 v dd io0 v dd io0 v dd io0 ? ? e2 0 (tl) 7 io pl2d pl2d pl2d pll_ck0c/hppll l12c_a1 e4 0 (tl) 7 io pl2c pl2c pl2c pll_ck0t/hppll l12t_a1 a2 ? ? vss vss vss vss ? ? e3 0 (tl) 7 io pl3d pl4d pl4d d5 l13c_a1 e1 0 (tl) 7 io pl3c pl4c pl4c d6 l13t_a1 f2 0 (tl) 8 io pl4d pl5d pl6d hdc l14c_d1 g4 0 (tl) 8 io pl4c pl5c pl6c ldc_n l14t_d1 a26 ? ? vss vss vss vss ? ? f3 0 (tl) 9 io pl5d pl6d pl8d testcfg l15c_a1 f1 0 (tl) 9 io pl5c pl6c pl8c d7 l15t_a1 g2 0 (tl) ? v dd io0 v dd io0 v dd io0 v dd io0 ? ? g1 0 (tl) 9 io pl5b pl7d pl9d vref_0_09 l16c_a1 g3 0 (tl) 9 io pl5a pl7c pl9c a17/ppc_a31 l16t_a1 h2 0 (tl) 9 io pl6d pl8d pl10d cs0_n l17c_d1 j4 0 (tl) 9 io pl6c pl8c pl10c cs1 l17t_d1 a c13 ? ? vss vss vss vss ? ? h1 0 (tl) 10 io pl7d pl10d pl12d init_n l18c_a1 h3 0 (tl) 10 io pl7c pl10c pl12c dout l18t_a1 aa4 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? j2 0 (tl) 10 io pl7b pl11d pl13d vref_0_10 l19c_a0 j1 0 (tl) 10 io pl7a pl11c pl13c a16/ppc_a30 l19t_a0 k2 7 (cl) 1 io pl8d pl12d pl14d a15/ppc_a29 l1c_d0 j3 7 (cl) 1 io pl8c pl12c pl14c a14/ppc_a28 l1t_d0 k1 7 (cl) 1 io pl9d pl13d pl16d vref_7_01 l2c_a2 k4 7 (cl) 1 io pl9c pl13c pl16c d4 l2t_a2 ad3 ? ? vss vss vss vss ? ? l2 7 (cl) 2 io pl10d pl14d pl18d rdy/busy_n/rclk l3c_d0 k3 7 (cl) 2 io pl10c pl14c pl18c vref_7_02 l3t_d0 l1 7 (cl) ? v dd io7 v dd io7 v dd io7 v dd io7 ? ? m2 7 (cl) 2 io pl10b pl15d pl19d a13/ppc_a27 l4c_a0 m1 7 (cl) 2 io pl10a pl15c pl19c a12/ppc_a26 l4t_a0
108 lattice semiconductor data sheet november, 2002 orca series 4 fpgas ae1 ? ? vss vss vss vss ? ? l3 7 (cl) 3 io pl11b pl17d pl21d a11/ppc_a25 l5c_d1 n2 7 (cl) 3 io pl11a pl17c pl21c vref_7_03 l5t_d1 a c11 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? m4 7 (cl) 4 io pl13d pl19d pl23d rd_n/mpi_strb_n l6c_d2 n1 7 (cl) 4 io pl13c pl19c pl23c vref_7_04 l6t_d2 ae2 ? ? vss vss vss vss ? ? m3 7 (cl) 4 io pl14d pl20d pl24d plck0c l7c_d1 p2 7 (cl) 4 io pl14c pl20c pl24c plck0t l7t_d1 p4 7 (cl) ? v dd io7 v dd io7 v dd io7 v dd io7 ? ? a c16 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? ae25 ? ? vss vss vss vss ? ? p1 7 (cl) 5 io pl15d pl21d pl25d a10/ppc_a24 l8c_d1 n3 7 (cl) 5 io pl15c pl21c pl25c a9/ppc_a23 l8t_d1 af1 ? ? vss vss vss vss ? ? r2 7 (cl) 5 io pl16d pl22d pl26d a8/ppc_a22 l9c_d0 p3 7 (cl) 5 io pl16c pl22c pl26c vref_7_05 l9t_d0 r1 7 (cl) 6 io pl17d pl24d pl28d plck1c l10c_d0 t2 7 (cl) 6 io pl17c pl24c pl28c plck1t l10t_d0 af25 ? ? vss vss vss vss ? ? r3 7 (cl) 6 io pl17b pl25d pl29d vref_7_06 l11c_d1 t1 7 (cl) 6 io pl17a pl25c pl29c a7/ppc_a21 l11t_d1 r4 7 (cl) 6 io pl18d pl26d pl30d a6/ppc_a20 l12c_d1 u2 7 (cl) 6 io pl18c pl26c pl30c a5/ppc_a19 l12t_d1 t3 7 (cl) ? v dd io7 v dd io7 v dd io7 v dd io7 ? ? u1 7 (cl) 7 io pl19d pl27d pl32d wr_n/mpi_rw l13c_a2 u4 7 (cl) 7 io pl19c pl27c pl32c vref_7_07 l13t_a2 v2 7 (cl) 8 io pl20d pl28d pl34d a4/ppc_a18 l14c_d1 u3 7 (cl) 8 io pl20c pl28c pl34c vref_7_08 l14t_d1 v1 7 (cl) 8 io pl20b pl29d pl35d a3/ppc_a17 l15c_d0 w2 7 (cl) 8 io pl20a pl29c pl35c a2/ppc_a16 l15t_d0 w1 7 (cl) 8 io pl21d pl30d pl36d a1/ppc_a15 l16c_d1 v3 7 (cl) 8 io pl21c pl30c pl36c a0/ppc_a14 l16t_d1 y2 7 (cl) 8 io pl21b pl31d pl37d dp0 l17c_d1 w4 7 (cl) 8 io pl21a pl31c pl37c dp1 l17t_d1 y1 6 (bl) 1 io pl22d pl32d pl38d d8 l1c_d1 w3 6 (bl) 1 io pl22c pl32c pl38c vref_6_01 l1t_d1 b25 ? ? vss vss vss vss ? ? aa2 6 (bl) 1 io pl22b pl33d pl39d d9 l2c_d1 y4 6 (bl) 1 io pl22a pl33c pl39c d10 l2t_d1 aa1 6 (bl) 2 io pl23c pl34c pl40c vref_6_02 ? y3 6 (bl) ? v dd io6 v dd io6 v dd io6 v dd io6 ? ? ab2 6 (bl) 3 io pl24d pl35b pl42d d11 l3c_a0 ab1 6 (bl) 3 io pl24c pl35a pl42c d12 l3t_a0 ta b le 67. 352-pin pbga pinout b a352 v dd io bank v ref group i/o or4e02 or4e04 or4e06 additional function p air
lattice semiconductor 109 data sheet november, 2002 orca series 4 fpgas b26 ? ? vss vss vss vss ? ? aa3 6 (bl) 3 io pl25d pl36b pl44d vref_6_03 l4c_d1 ac 26 (bl) 3 io pl25c pl36a pl44c d13 l4t_d1 c24 ? ? vss vss vss vss ? ? ab4 6 (bl) 4 io pl27d pl39d pl47d pll_ck7c/hppll l5c_d2 ac 16 (bl) 4 io pl27c pl39c pl47c pll_ck7t/hppll l5t_d2 c3 ? ? vss vss vss vss ? ? d14 ? ? vss vss vss vss ? ? ab3 ? ? i ptemp ptemp ptemp ptemp ? ad2 6 (bl) ? v dd io6 v dd io6 v dd io6 v dd io6 ? ? a c21 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? ac 3? ?i ol vds_r lvds_r lvds_r lvds_r ? ad1 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? d19 ? ? vss vss vss vss ? ? af2 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? ac6 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? ae3 6 (bl) 5 io pb2a pb2a pb2a dp2 ? af3 6 (bl) 5 io pb2c pb2c pb2c pll_ck6t/ppll l6t_a0 ae4 6 (bl) 5 io pb2d pb2d pb2d pll_ck6c/ppll l6c_a0 ad4 6 (bl) 5 io pb3c pb4a pb4c vref_6_05 l7t_a1 af4 6 (bl) 5 io pb3d pb4b pb4d dp3 l7c_a1 d23 ? ? vss vss vss vss ? ? ae5 6 (bl) 6 io pb4c pb5c pb6c vref_6_06 l8t_a1 ac 56 (bl) 6 io pb4d pb5d pb6d d14 l8c_a1 ad5 6 (bl) ? v dd io6 v dd io6 v dd io6 v dd io6 ? ? af5 6 (bl) 7 io pb5c pb6c pb8c d15 l9t_d0 ae6 6 (bl) 7 io pb5d pb6d pb8d d16 l9c_d0 ac 76 (bl) 7 io pb6a pb7c pb9c d17 l10t_d0 ad6 6 (bl) 7 io pb6b pb7d pb9d d18 l10c_d0 d4 ? ? vss vss vss vss ? ? af6 6 (bl) 7 io pb6c pb8c pb10c vref_6_07 l11t_d0 ae7 6 (bl) 7 io pb6d pb8d pb10d d19 l11c_d0 af7 6 (bl) 8 io pb7a pb9c pb11c d20 l12t_a1 ad7 6 (bl) 8 io pb7b pb9d pb11d d21 l12c_a1 ae8 6 (bl) 8 io pb7c pb10c pb12c vref_6_08 l13t_d1 ac 96 (bl) 8 io pb7d pb10d pb12d d22 l13c_d1 d9 ? ? vss vss vss vss ? ? af8 6 (bl) 9 io pb8c pb11c pb13c d23 l14t_a1 ad8 6 (bl) 9 io pb8d pb11d pb13d d24 l14c_a1 ae9 6 (bl) 9 io pb9c pb12c pb14c vref_6_09 l15t_a0 af9 6 (bl) 9 io pb9d pb12d pb14d d25 l15c_a0 ae10 6 (bl) 10 io pb10c pb13c pb16c d26 l16t_d0 ad9 6 (bl) 10 io pb10d pb13d pb16d d27 l16c_d0 af10 6 (bl) ? v dd io6 v dd io6 v dd io6 v dd io6 ? ? ta b le 67. 352-pin pbga pinout b a352 v dd io bank v ref group i/o or4e02 or4e04 or4e06 additional function p air
110 lattice semiconductor data sheet november, 2002 orca series 4 fpgas a c10 6 (bl) 10 io pb11c pb14c pb18c vref_6_10 l17t_d1 ae11 6 (bl) 10 io pb11d pb14d pb18d d28 l17c_d1 ad10 6 (bl) 11 io pb12a pb15c pb19c d29 l18t_d1 af11 6 (bl) 11 io pb12b pb15d pb19d d30 l18c_d1 ae12 6 (bl) 11 io pb12c pb16c pb20c vref_6_11 l19t_a0 af12 6 (bl) 11 io pb12d pb16d pb20d d31 l19c_a0 ad11 5 (bc) 1 io pb13a pb17c pb21c ? l1t_d1 ae13 5 (bc) 1 io pb13b pb17d pb21d ? l1c_d1 d11 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? a c12 5 (bc) 1 io pb13c pb18c pb22c vref_5_01 l2t_d2 af13 5 (bc) 1 io pb13d pb18d pb22d ? l2c_d2 h4 ? ? vss vss vss vss ? ? ad12 5 (bc) 2 io pb14c pb19c pb23c pbck0t l3t_d1 ae14 5 (bc) 2 io pb14d pb19d pb23d pbck0c l3c_d1 a c14 5 (bc) ? v dd io5 v dd io5 v dd io5 v dd io5 ? ? af14 5 (bc) 2 io pb15c pb20c pb24c vref_5_02 l4t_d1 ad13 5 (bc) 2 io pb15d pb20d pb24d ? l4c_d1 d16 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? ae15 5 (bc) 3 io pb16c pb21c pb26c ? l5t_d0 ad14 5 (bc) 3 io pb16d pb21d pb26d vref_5_03 l5c_d0 af15 5 (bc) 3 io pb17a pb22c pb27c ? l6t_d0 ae16 5 (bc) 3 io pb17b pb22d pb27d ? l6c_d0 j23 ? ? vss vss vss vss ? ? ad15 5 (bc) 3 io pb17c pb23c pb28c pbck1t l7t_d1 af16 5 (bc) 3 io pb17d pb23d pb28d pbck1c l7c_d1 a c15 5 (bc) 4 io pb18a pb24c pb29c ? l8t_d1 ae17 5 (bc) 4 io pb18b pb24d pb29d ? l8c_d1 ad16 5 (bc) ? v dd io5 v dd io5 v dd io5 v dd io5 ? ? af17 5 (bc) 4 io pb18c pb25c pb30c ? l9t_a2 a c17 5 (bc) 4 io pb18d pb25d pb30d vref_5_04 l9c_a2 n4 ? ? vss vss vss vss ? ? p23 ? ? vss vss vss vss ? ? ae18 5 (bc) 5 io pb19c pb26c pb32c ? l10t_d0 ad17 5 (bc) 5 io pb19d pb26d pb32d vref_5_05 l10c_d0 af18 5 (bc) 5 io pb20c pb27c pb34c ? l11t_d0 ae19 5 (bc) 5 io pb20d pb27d pb34d ? l11c_d0 af19 5 (bc) 6 io pb21a pb28c pb35c ? l12t_d1 ad18 5 (bc) 6 io pb21b pb28d pb35d vref_5_06 l12c_d1 ae20 4 (br) 1 io pb22a pb30c pb37c ? l1t_d1 a c19 4 (br) 1 io pb22b pb30d pb37d ? l1c_d1 l13 ? ? vss vss vss vss ? ? af20 4 (br) 1 io pb22c pb31c pb38c vref_4_01 l2t_d1 ad19 4 (br) 1 io pb22d pb31d pb38d ? l2c_d1 ae21 4 (br) 1 io pb23a pb32c pb39c ? l3t_d1 ta b le 67. 352-pin pbga pinout b a352 v dd io bank v ref group i/o or4e02 or4e04 or4e06 additional function p air
lattice semiconductor 111 data sheet november, 2002 orca series 4 fpgas a c20 4 (br) 1 io pb23b pb32d pb39d ? l3c_d1 af21 4 (br) ? v dd io4 v dd io4 v dd io4 v dd io4 ? ? ad20 4 (br) 2 io pb23c pb33c pb40c ? l4t_d1 ae22 4 (br) 2 io pb23d pb33d pb40d vref_4_02 l4c_d1 l14 ? ? vss vss vss vss ? ? af22 4 (br) 2 io pb24c pb34c pb42c ? ? ad21 4 (br) 3 io pb25a pb35a pb43a ? ? ae23 4 (br) 3 io pb25c pb35c pb44c ? l5t_d1 a c22 4 (br) 3 io pb25d pb35d pb44d vref_4_03 l5c_d1 l15 ? ? vss vss vss vss ? ? af23 4 (br) 3 io pb26c pb36c pb45c ? l6t_d1 ad22 4 (br) 3 io pb26d pb36d pb45d ? l6c_d1 l16 ? ? vss vss vss vss ? ? ae24 4 (br) 4 io pb27c pb37c pb47c pll_ck5t/ppll l7t_d0 ad23 4 (br) 4 io pb27d pb37d pb47d pll_ck5c/ppll l7c_d0 d21 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? af24 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? m11 ? ? vss vss vss vss ? ? m12 ? ? vss vss vss vss ? ? d6 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? ae26 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? ad25 4 (br) ? v dd io4 v dd io4 v dd io4 v dd io4 ? ? ad26 4 (br) 5 io pr26a pr38a pr46c pll_ck4t/pll2 l8t_d0 a c25 4 (br) 5 io pr26b pr38b pr46d pll_ck4c/pll2 l8c_d0 m13 ? ? vss vss vss vss ? ? a c24 4 (br) 5 io pr25a pr37a pr44c vref_4_05 l9t_a1 a c26 4 (br) 5 io pr25b pr37b pr44d ? l9c_a1 m14 ? ? vss vss vss vss ? ? ab25 4 (br) 6 io pr25c pr36a pr43c ? l10t_a1 ab23 4 (br) 6 io pr25d pr36b pr43d ? l10c_a1 ab24 4 (br) ? v dd io4 v dd io4 v dd io4 v dd io4 ? ? ab26 4 (br) 6 io pr24c pr35c pr41c vref_4_06 l11t_d0 aa25 4 (br) 6 io pr24d pr35d pr41d ? l11c_d0 y23 4 (br) 7 io pr23a pr34c pr40c ? l12t_d0 aa24 4 (br) 7 io pr23b pr34d pr40d ? l12c_d0 m15 ? ? vss vss vss vss ? ? aa26 4 (br) 7 io pr23c pr33c pr39c ? l13t_d0 y25 4 (br) 7 io pr23d pr33d pr39d vref_4_07 l13c_d0 y26 4 (br) 7 io pr22a pr32c pr38c ? l14t_a1 y24 4 (br) 7 io pr22b pr32d pr38d ? l14c_a1 w25 4 (br) 8 io pr22c pr31c pr37c ? l15t_d1 v23 4 (br) 8 io pr22d pr31d pr37d vref_4_08 l15c_d1 w26 4 (br) 8 io pr21c pr30c pr36c ? l16t_a1 w24 4 (br) 8 io pr21d pr30d pr36d ? l16c_a1 ta b le 67. 352-pin pbga pinout b a352 v dd io bank v ref group i/o or4e02 or4e04 or4e06 additional function p air
112 lattice semiconductor data sheet november, 2002 orca series 4 fpgas v25 3 (cr) 1 io pr20c pr29c pr35c ? l1t_a0 v26 3 (cr) 1 io pr20d pr29d pr35d ? l1c_a0 m16 ? ? vss vss vss vss ? ? u25 3 (cr) 1 io pr19c pr28c pr33c vref_3_01 l2t_d0 v24 3 (cr) 1 io pr19d pr28d pr33d ? l2c_d0 u26 3 (cr) ? v dd io3 v dd io3 v dd io3 v dd io3 ? ? u23 3 (cr) 2 io pr18c pr26a pr31c ? l3t_d1 t25 3 (cr) 2 io pr18d pr26b pr31d vref_3_02 l3c_d1 u24 3 (cr) 2 io pr17a pr25a pr30c ? l4t_d1 t26 3 (cr) 2 io pr17b pr25b pr30d ? l4c_d1 n11 ? ? vss vss vss vss ? ? r25 3 (cr) 3 io pr17c pr25c pr29c ? l5t_a0 r26 3 (cr) 3 io pr17d pr25d pr29d vref_3_03 l5c_a0 f23 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? t24 3 (cr) 4 io pr16c pr23c pr27c prck1t l6t_d1 p25 3 (cr) 4 io pr16d pr23d pr27d prck1c l6c_d1 r23 3 (cr) 4 io pr15a pr22c pr26c ? l7t_d2 p26 3 (cr) 4 io pr15b pr22d pr26d vref_3_04 l7c_d2 r24 3 (cr) ? v dd io3 v dd io3 v dd io3 v dd io3 ? ? n25 3 (cr) 5 io pr15c pr21c pr25c ? l8t_a1 n23 3 (cr) 5 io pr15d pr21d pr25d ? l8c_a1 n12 ? ? vss vss vss vss ? ? f4 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? n26 3 (cr) 5 io pr14a pr20c pr24c prck0t l9t_d1 p24 3 (cr) 5 io pr14b pr20d pr24d prck0c l9c_d1 m25 3 (cr) 5 io pr14c pr19c pr23c vref_3_05 l10t_d0 n24 3 (cr) 5 io pr14d pr19d pr23d ? l10c_d0 n13 ? ? vss vss vss vss ? ? m26 3 (cr) 6 io pr13c pr17c pr21c ? l11t_d0 l25 3 (cr) 6 io pr13d pr17d pr21d vref_3_06 l11c_d0 m24 3 (cr) 6 io pr12a pr16c pr20c ? l12t_d1 l26 3 (cr) 6 io pr12b pr16d pr20d ? l12c_d1 m23 3 (cr) ? v dd io3 v dd io3 v dd io3 v dd io3 ? ? k25 3 (cr) 7 io pr12c pr15a pr19c ? l13t_d0 l24 3 (cr) 7 io pr12d pr15b pr19d ? l13c_d0 k26 3 (cr) 7 io pr11b pr14b pr18d ? ? n14 ? ? vss vss vss vss ? ? k23 3 (cr) 7 io pr11c pr14c pr17c vref_3_07 l14t_d1 j25 3 (cr) 7 io pr11d pr14d pr17d ? l14c_d1 k24 3 (cr) 8 io pr10c pr13c pr15c ? l15t_d1 j26 3 (cr) 8 io pr10d pr13d pr15d ? l15c_d1 n15 ? ? vss vss vss vss ? ? h25 3 (cr) 8 io pr9c pr12c pr14c vref_3_08 l16t_a0 h26 3 (cr) 8 io pr9d pr12d pr14d ? l16c_a0 ta b le 67. 352-pin pbga pinout b a352 v dd io bank v ref group i/o or4e02 or4e04 or4e06 additional function p air
lattice semiconductor 113 data sheet november, 2002 orca series 4 fpgas l23 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? j24 2 (tr) 1 io pr8c pr11c pr13c ? l1t_d1 g25 2 (tr) 1 io pr8d pr11d pr13d vref_2_01 l1c_d1 h23 2 (tr) 1 io pr7a pr10c pr12c ? l2t_d2 g26 2 (tr) 1 io pr7b pr10d pr12d ? l2c_d2 p12 ? ? vss vss vss vss ? ? h24 2 (tr) 1 io pr7c pr9c pr11c ? l3t_d1 f25 2 (tr) 1 io pr7d pr9d pr11d ? l3c_d1 g23 2 (tr) 2 io pr6a pr7a pr10c ? l4t_d2 f26 2 (tr) 2 io pr6b pr7b pr10d ? l4c_d2 g24 2 (tr) ? v dd io2 v dd io2 v dd io2 v dd io2 ? ? e25 2 (tr) 2 io pr6c pr6a pr9c vref_2_02 l5t_a0 e26 2 (tr) 2 io pr6d pr6b pr9d ? l5c_a0 p13 ? ? vss vss vss vss ? ? f24 2 (tr) 3 io pr5c pr5a pr7c ? l6t_d1 d25 2 (tr) 3 io pr5d pr5b pr7d vref_2_03 l6c_d1 e23 2 (tr) 3 io pr4c pr4c pr5c ? l7t_d2 d26 2 (tr) 3 io pr4d pr4d pr5d ? l7c_d2 p14 ? ? vss vss vss vss ? ? e24 2 (tr) 4 io pr3c pr3c pr3c pll_ck3t/pll1 l8t_d1 c25 2 (tr) 4 io pr3d pr3d pr3d pll_ck3c/pll1 l8c_d1 d24 2 (tr) ? v dd io2 v dd io2 v dd io2 v dd io2 ? ? c26 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? l4 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? p15 ? ? vss vss vss vss ? ? p16 ? ? vss vss vss vss ? ? a25 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? b24 ? ? io pll_vf pll_vf pll_vf pll_vf ? a24 2 (tr) 5 io pt27d pt37d pt47d pll_ck2c/ppll l9c_a0 b23 2 (tr) 5 io pt27c pt37c pt47c pll_ck2t/ppll l9t_a0 r11 ? ? vss vss vss vss ? ? c23 2 (tr) 5 io pt26d pt36d pt45d vref_2_05 l10c_a1 a23 2 (tr) 5 io pt26c pt36c pt45c ? l10t_a1 b22 2 (tr) 6 io pt26b pt35b pt43d ? l11c_a1 d22 2 (tr) 6 io pt26a pt35a pt43c ? l11t_a1 c22 2 (tr) 6 io pt25d pt34d pt42d vref_2_06 l12c_a1 a22 2 (tr) 6 io pt25c pt34c pt42c ? l12t_a1 r12 ? ? vss vss vss vss ? ? b21 2 (tr) 7 io pt24d pt33d pt40d ? l13c_d1 d20 2 (tr) 7 io pt24c pt33c pt40c vref_2_07 l13t_d1 c21 2 (tr) ? v dd io2 v dd io2 v dd io2 v dd io2 ? ? a21 2 (tr) 7 io pt24b pt32d pt39d ? l14c_d0 b20 2 (tr) 7 io pt24a pt32c pt39c ? l14t_d0 a20 2 (tr) 8 io pt23d pt31d pt38d ? l15c_a1 ta b le 67. 352-pin pbga pinout b a352 v dd io bank v ref group i/o or4e02 or4e04 or4e06 additional function p air
114 lattice semiconductor data sheet november, 2002 orca series 4 fpgas c20 2 (tr) 8 io pt23c pt31c pt38c vref_2_08 l15t_a1 r13 ? ? vss vss vss vss ? ? b19 2 (tr) 8 io pt22d pt29d pt36d ? l16c_d1 d18 2 (tr) 8 io pt22c pt29c pt36c ? l16t_d1 a19 1 (tc) 1 io pt21d pt28d pt35d ? l1c_a1 c19 1 (tc) 1 io pt21c pt28c pt35c ? l1t_a1 r15 ? ? vss vss vss vss ? ? b18 1 (tc) 1 io pt20d pt27d pt34d vref_1_01 l2c_a0 a18 1 (tc) 1 io pt20c pt27c pt34c ? l2t_a0 b17 1 (tc) 1 io pt20b pt27b pt33d ? l3c_d0 c18 1 (tc) 1 io pt20a pt27a pt33c ? l3t_d0 a17 1 (tc) 2 io pt19d pt26d pt32d ? l4c_a2 d17 1 (tc) 2 io pt19c pt26c pt32c vref_1_02 l4t_a2 r16 ? ? vss vss vss vss ? ? t11 ? ? vss vss vss vss ? ? t23 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? b16 1 (tc) 2 io pt18d pt25d pt30d ? l5c_d0 c17 1 (tc) 2 io pt18c pt25c pt30c ? l5t_d0 a16 1 (tc) ? v dd io1 v dd io1 v dd io1 v dd io1 ? ? b15 1 (tc) 3 io pt18b pt24d pt29d ? l6c_a0 a15 1 (tc) 3 io pt18a pt24c pt29c vref_1_03 l6t_a0 c16 1 (tc) 3 io pt17d pt23d pt28d ? l7c_d1 b14 1 (tc) 3 io pt17c pt23c pt28c ? l7t_d1 t12 ? ? vss vss vss vss ? ? d15 1 (tc) 4 io pt16d pt21d pt26d ? l8c_d2 a14 1 (tc) 4 io pt16c pt21c pt26c ? l8t_d2 t4 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? c15 1 (tc) 4 io pt15d pt19d pt24d ? l9c_d1 b13 1 (tc) 4 io pt15c pt19c pt24c vref_1_04 l9t_d1 d13 1 (tc) ? v dd io1 v dd io1 v dd io1 v dd io1 ? ? a13 1 (tc) 5 io pt14d pt18d pt23d ptck1c l10c_d1 c14 1 (tc) 5 io pt14c pt18c pt23c ptck1t l10t_d1 t13 ? ? vss vss vss vss ? ? b12 1 (tc) 5 io pt13d pt17d pt22d ptck0c l11c_d0 c13 1 (tc) 5 io pt13c pt17c pt22c ptck0t l11t_d0 a12 1 (tc) 5 io pt13b pt16d pt21d vref_1_05 l12c_d0 b11 1 (tc) 5 io pt13a pt16c pt21c ? l12t_d0 t14 ? ? vss vss vss vss ? ? c12 1 (tc) 6 io pt12b pt14d pt19d ? l13c_d1 a11 1 (tc) 6 io pt12a pt14c pt19c vref_1_06 l13t_d1 d12 0 (tl) 1 io pt11d pt13d pt18d mpi_rtry_n l1c_d2 b10 0 (tl) 1 io pt11c pt13c pt18c mpi_ack_n l1c_d2 c11 0 (tl) ? v dd io0 v dd io0 v dd io0 v dd io0 ? ? a10 0 (tl) 1 io pt10d pt12d pt16d m0 l2c_a2 ta b le 67. 352-pin pbga pinout b a352 v dd io bank v ref group i/o or4e02 or4e04 or4e06 additional function p air
lattice semiconductor 115 data sheet november, 2002 orca series 4 fpgas d10 0 (tl) 1 io pt10c pt12c pt16c m1 l2t_a2 a c18 ? ? vss vss vss vss ? ? b9 0 (tl) 2 io pt10b pt12b pt15d mpi_clk l3c_d0 c10 0 (tl) 2 io pt10a pt12a pt15c a21/mpi_burst_n l3c_d0 a9 0 (tl) 2 io pt9d pt11d pt14d m2 l4c_d0 b8 0 (tl) 2 io pt9c pt11c pt14c m3 l4t_d0 a8 0 (tl) 2 io pt9b pt11b pt13d vref_0_02 l5c_d1 c9 0 (tl) 2 io pt9a pt11a pt13c mpi_tea_n l5t_d1 b7 0 (tl) 3 io pt8b pt9d pt11d vref_0_03 ? d8 0 (tl) 3 io pt7d pt8d pt10d d0 l6c_d2 a7 0 (tl) 3 io pt7c pt8c pt10c tms l6t_d2 a c23 ? ? vss vss vss vss ? ? c8 0 (tl) 4 io pt7b pt7d pt9d a20/mpi_bdip_n l7c_d2 b6 0 (tl) 4 io pt7a pt7c pt9c a19/mpi_tsz1 l7t_d2 d7 0 (tl) 4 io pt6d pt6d pt8d a18/mpi_tsz0 l8c_d2 a6 0 (tl) 4 io pt6c pt6c pt8c d3 l8t_d2 c7 0 (tl) ? v dd io0 v dd io0 v dd io0 v dd io0 ? ? b5 0 (tl) 5 io pt5d pt5d pt6d d1 l9c_a0 a5 0 (tl) 5 io pt5c pt5c pt6c d2 l9t_a0 ac4 ? ? vss vss vss vss ? ? c6 0 (tl) 5 io pt4d pt4d pt4d tdi l10c_d2 b4 0 (tl) 5 io pt4c pt4c pt4c tck l10t_d2 ac8 ? ? vss vss vss vss ? ? d5 0 (tl) 6 io pt2d pt2d pt2d pll_ck1c/ppll l11c_d2 a4 0 (tl) 6 io pt2c pt2c pt2c pll_ck1t/ppll l11t_d2 c5 ? ? o pcfg_ mpi_irq pcfg_ mpi_irq pcfg_ mpi_irq cfg_irq_n/ mpi_irq_n ? b3 ? ? io pcclk pcclk pcclk cclk ? c4 ? ? io pdone pdone pdone done ? a3 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? ad24 ? ? vss vss vss vss ? ? af26 ? ? vss vss vss vss ? ? b2 ? ? vss vss vss vss ? ? v4 ? ? vss vss vss vss ? ? w23 ? ? vss vss vss vss ? ? l11 ? ? vss vss vss vss ? ? l12 ? ? vss vss vss vss ? ? n16 ? ? vss vss vss vss ? ? p11 ? ? vss vss vss vss ? ? r14 ? ? vss vss vss vss ? ? t15 ? ? vss vss vss vss ? ? t16 ? ? vss vss vss vss ? ? ta b le 67. 352-pin pbga pinout b a352 v dd io bank v ref group i/o or4e02 or4e04 or4e06 additional function p air
116 lattice semiconductor data sheet november, 2002 orca series 4 fpgas 416-pin bgam pinout ta b le 68. 416-pin bgam pinout bm416 v dd io bank vref group i/o or4e02 or4e04 additional function p air a2 ? ? vss vss vss ? ? d4 ? ? v dd 33 v dd 33 v dd 33 ? ? d3 ? ? o prd_data prd_data rd_data/tdo ? a1 ? ? v dd 15 v dd 15 v dd 15 ? ? c1 ? ? i preset_n preset_n reset_n ? e4 ? ? i prd_cfg_ n prd_cfg_n rd_cfg_n ? f4 ? ? i pprgrm_n pprgrm_n prgrm_n ? c2 0 (tl) ? v dd io0 v dd io0 v dd io0 ? ? d2 0 (tl) 7 io pl2d pl2d pll_ck0c/hppll l14c_d0 e3 0 (tl) 7 io pl2c pl2c pll_ck0t/hppll l14t_d0 a25 ? ? vss vss vss ? ? d1 0 (tl) 7 io pl2a pl3c vref_0_07 ? e2 0 (tl) 7 io pl3d pl4d d5 l15c_d0 f3 0 (tl) 7 io pl3c pl4c d6 l15t_d0 e1 0 (tl) 8 io pl4d pl5d hdc l16c_d0 f2 0 (tl) 8 io pl4c pl5c ldc_n l16t_d0 b1 ? ? vss vss vss ? ? g4 0 (tl) 9 io pl5d pl6d testcfg l17c_a0 h4 0 (tl) 9 io pl5c pl6c d7 l17t_a0 g3 0 (tl) ? v dd io0 v dd io0 v dd io0 ? ? f1 0 (tl) 9 io pl5b pl7d vref_0_09 l18c_d0 g2 0 (tl) 9 io pl5a pl7c a17/ppc_a31 l18t_d0 h2 0 (tl) 9 io pl6d pl8d cs0_n l19c_a0 h3 0 (tl) 9 io pl6c pl8c cs1 l19t_a0 g1 0 (tl) 10 io pl6b pl9d ? l20c_a0 h1 0 (tl) 10 io pl6a pl9c ? l20t_a0 j4 0 (tl) 10 io pl7d pl10d init_n l21c_a0 k4 0 (tl) 10 io pl7c pl10c dout l21t_a0 a26 ? ? v dd 15 v dd 15 v dd 15 ? ? j3 0 (tl) 10 io pl7b pl11d vref_0_10 l22c_a0 j2 0 (tl) 10 io pl7a pl11c a16/ppc_a30 l22t_a0 j1 7 (cl) 1 io pl8d pl12d a15/ppc_a29 l1c_d0 k2 7 (cl) 1 io pl8c pl12c a14/ppc_a28 l1t_d0 k1 7 (cl) ? v dd io7 v dd io7 v dd io7 ? ? k3 7 (cl) 1 io pl9d pl13d vref_7_01 l2c_a0 l3 7 (cl) 1 io pl9c pl13c d4 l2t_a0 u16 ? ? vss vss vss ? ? l4 7 (cl) 2 io pl10d pl14d rdy/busy_n/ rclk l3c_a0 m4 7 (cl) 2 io pl10c pl14c vref_7_02 l3t_a0 l2 7 (cl) ? v dd io7 v dd io7 v dd io7 ? ? l1 7 (cl) 2 io pl10b pl15d a13/ppc_a27 l4c_a0
lattice semiconductor 117 data sheet november, 2002 orca series 4 fpgas m1 7 (cl) 2 io pl10a pl15c a12/ppc_a26 l4t_a0 m3 7 (cl) 3 io pl11d pl16d ? l5c_a0 m2 7 (cl) 3 io pl11c pl16c ? l5t_a0 u17 ? ? vss vss vss ? ? n1 7 (cl) 3 io pl11b pl17d a11/ppc_a25 l6c_a0 n2 7 (cl) 3 io pl11a pl17c vref_7_03 l6t_a0 u14 ? ? v dd 15 v dd 15 v dd 15 ? ? n3 7 (cl) 4 io pl13d pl19d rd_n/ mpi_strb_n l7c_a0 n4 7 (cl) 4 io pl13c pl19c vref_7_04 l7t_a0 ae1 ? ? vss vss vss ? ? p4 7 (cl) 4 io pl14d pl20d plck0c l8c_a0 p3 7 (cl) 4 io pl14c pl20c plck0t l8t_a0 p2 7 (cl) ? v dd io7 v dd io7 v dd io7 ? ? ae26 ? ? vss vss vss ? ? p1 7 (cl) 5 io pl15d pl21d a10/ppc_a24 l9c_a0 r1 7 (cl) 5 io pl15c pl21c a9/ppc_a23 l9t_a0 af2 ? ? vss vss vss ? ? r2 7 (cl) 5 io pl16d pl22d a8/ppc_a22 l10c_a0 r3 7 (cl) 5 io pl16c pl22c vref_7_05 l10t_a0 af1 ? ? v dd 15 v dd 15 v dd 15 ? ? t1 7 (cl) 6 io pl17d pl24d plck1c l11c_a0 t2 7 (cl) 6 io pl17c pl24c plck1t l11t_a0 af25 ? ? vss vss vss ? ? t4 7 (cl) 6 io pl17b pl25d vref_7_06 l12c_a0 r4 7 (cl) 6 io pl17a pl25c a7/ppc_a21 l12t_a0 u1 7 (cl) 6 io pl18d pl26d a6/ppc_a20 l13c_a0 u2 7 (cl) 6 io pl18c pl26c a5/ppc_a19 l13t_a0 t3 7 (cl) ? v dd io7 v dd io7 v dd io7 ? ? v1 7 (cl) 7 io pl18b pl26b ? ? v2 7 (cl) 7 io pl19d pl27d wr_n/mpi_rw l14c_d0 u3 7 (cl) 7 io pl19c pl27c vref_7_07 l14t_d0 af26 ? ? v dd 15 v dd 15 v dd 15 ? ? w1 7 (cl) 8 io pl20d pl28d a4/ppc_a18 l15c_a0 y1 7 (cl) 8 io pl20c pl28c vref_7_08 l15t_a0 v4 7 (cl) 8 io pl20b pl29d a3/ppc_a17 l16c_a0 u4 7 (cl) 8 io pl20a pl29c a2/ppc_a16 l16t_a0 v3 7 (cl) 8 io pl21d pl30d a1/ppc_a15 l17c_d0 w2 7 (cl) 8 io pl21c pl30c a0/ppc_a14 l17t_d0 y2 7 (cl) 8 io pl21b pl31d dp0 l18c_d0 w3 7 (cl) 8 io pl21a pl31c dp1 l18t_d0 aa1 6 (bl) 1 io pl22d pl32d d8 l1c_a0 aa2 6 (bl) 1 io pl22c pl32c vref_6_01 l1t_a0 t16 ? ? vss vss vss ? ? ta b le 68. 416-pin bgam pinout bm416 v dd io bank vref group i/o or4e02 or4e04 additional function p air
118 lattice semiconductor data sheet november, 2002 orca series 4 fpgas y3 6 (bl) 1 io pl22b pl33d d9 l2c_d0 w4 6 (bl) 1 io pl22a pl33c d10 l2t_d0 y4 6 (bl) 2 io pl23d pl34d ? l3c_d0 aa3 6 (bl) 2 io pl23c pl34c vref_6_02 l3t_d0 ab1 6 (bl) ? v dd io6 v dd io6 v dd io6 ? ? ab2 6 (bl) 3 io pl24d pl35b d11 l4c_d0 ac 16 (bl) 3 io pl24c pl35a d12 l4t_d0 t17 ? ? vss vss vss ? ? ac 26 (bl) 3 io pl25d pl36b vref_6_03 l5c_d0 ab3 6 (bl) 3 io pl25c pl36a d13 l5t_d0 ad1 6 (bl) 4 io pl26c pl37a vref_6_04 ? u10 ? ? vss vss vss ? ? aa4 6 (bl) 4 io pl27d pl39d pll_ck7c/hppll l6c_a0 ab4 6 (bl) 4 io pl27c pl39c pll_ck7t/hppll l6t_a0 u11 ? ? vss vss vss ? ? u12 ? ? vss vss vss ? ? ac 3? ?i ptemp ptemp ptemp ? ad2 6 (bl) ? v dd io6 v dd io6 v dd io6 ? ? r14 ? ? v dd 15 v dd 15 v dd 15 ? ? ae2 ? ? io lvds_r lvds_r lvds_r ? ad3 ? ? v dd 33 v dd 33 v dd 33 ? ? u15 ? ? vss vss vss ? ? ac4 ? ? v dd 33 v dd 33 v dd 33 ? ? t13 ? ? v dd 15 v dd 15 v dd 15 ? ? ae3 6 (bl) 5 io pb2a pb2a dp2 ? ac 56 (bl) 5 io pb2c pb2c pll_ck6t/ppll l7t_d0 ad4 6 (bl) 5 io pb2d pb2d pll_ck6c/ppll l7c_d0 ae4 6 (bl) 5 io pb3c pb4a vref_6_05 l8t_d0 af3 6 (bl) 5 io pb3d pb4b dp3 l8c_d0 ac 66 (bl) 6 io pb4a pb4c ? l9t_d0 ad5 6 (bl) 6 io pb4b pb4d ? l9c_d0 af4 6 (bl) 6 io pb4c pb5c vref_6_06 l10t_d0 ae5 6 (bl) 6 io pb4d pb5d d14 l10c_d0 ad6 6 (bl) 6 io pb5b pb6b ? ? af5 6 (bl) ? v dd io6 v dd io6 v dd io6 ? ? ac 76 (bl) 7 io pb5c pb6c d15 l11t_a0 ac 86 (bl) 7 io pb5d pb6d d16 l11c_a0 ad7 6 (bl) 7 io pb6a pb7c d17 l12t_d0 ae6 6 (bl) 7 io pb6b pb7d d18 l12c_d0 ae7 6 (bl) 7 io pb6c pb8c vref_6_07 l13t_d0 ad8 6 (bl) 7 io pb6d pb8d d19 l13c_d0 af6 6 (bl) 8 io pb7a pb9c d20 l14t_a0 af7 6 (bl) 8 io pb7b pb9d d21 l14c_a0 t14 ? ? v dd 15 v dd 15 v dd 15 ? ? ta b le 68. 416-pin bgam pinout bm416 v dd io bank vref group i/o or4e02 or4e04 additional function p air
lattice semiconductor 119 data sheet november, 2002 orca series 4 fpgas ae8 6 (bl) 8 io pb7c pb10c vref_6_08 l15t_d0 ad9 6 (bl) 8 io pb7d pb10d d22 l15c_d0 ac 96 (bl) 9 io pb8c pb11c d23 l16t_a0 a c10 6 (bl) 9 io pb8d pb11d d24 l16c_a0 af8 6 (bl) 9 io pb9c pb12c vref_6_09 l17t_d0 ae9 6 (bl) 9 io pb9d pb12d d25 l17c_d0 ad10 6 (bl) 10 io pb10c pb13c d26 l18t_a0 ae10 6 (bl) 10 io pb10d pb13d d27 l18c_a0 af9 6 (bl) ? v dd io6 v dd io6 v dd io6 ? ? ae11 6 (bl) 10 io pb11c pb14c vref_6_10 l19t_a0 ad11 6 (bl) 10 io pb11d pb14d d28 l19c_a0 a c12 6 (bl) 11 io pb12a pb15c d29 l20t_a0 a c11 6 (bl) 11 io pb12b pb15d d30 l20c_a0 af10 6 (bl) 11 io pb12c pb16c vref_6_11 l21t_a0 af11 6 (bl) 11 io pb12d pb16d d31 l21c_a0 ad12 5 (bc) 1 io pb13a pb17c ? l1t_a0 ae12 5 (bc) 1 io pb13b pb17d ? l1c_a0 p16 ? ? v dd 15 v dd 15 v dd 15 ? ? af12 5 (bc) 1 io pb13c pb18c vref_5_01 l2t_a0 af13 5 (bc) 1 io pb13d pb18d ? l2c_a0 r16 ? ? vss vss vss ? ? ad13 5 (bc) 2 io pb14c pb19c pbck0t l3t_a0 ae13 5 (bc) 2 io pb14d pb19d pbck0c l3c_a0 af14 5 (bc) ? v dd io5 v dd io5 v dd io5 ? ? a c14 5 (bc) 2 io pb15c pb20c vref_5_02 l4t_a0 a c13 5 (bc) 2 io pb15d pb20d ? l4c_a0 p17 ? ? v dd 15 v dd 15 v dd 15 ? ? ae14 5 (bc) 3 io pb16c pb21c ? l5t_a0 ad14 5 (bc) 3 io pb16d pb21d vref_5_03 l5c_a0 af15 5 (bc) 3 io pb17a pb22c ? l6t_a0 ae15 5 (bc) 3 io pb17b pb22d ? l6c_a0 r17 ? ? vss vss vss ? ? ad15 5 (bc) 3 io pb17c pb23c pbck1t l7t_d0 ae16 5 (bc) 3 io pb17d pb23d pbck1c l7c_d0 a c15 5 (bc) 4 io pb18a pb24c ? l8t_a0 a c16 5 (bc) 4 io pb18b pb24d ? l8c_a0 af17 5 (bc) ? v dd io5 v dd io5 v dd io5 ? ? ad16 5 (bc) 4 io pb18c pb25c ? l9t_d0 ae17 5 (bc) 4 io pb18d pb25d vref_5_04 l9c_d0 t10 ? ? vss vss vss ? ? t11 ? ? vss vss vss ? ? af18 5 (bc) 5 io pb19c pb26c ? l10t_a0 ae18 5 (bc) 5 io pb19d pb26d vref_5_05 l10c_a0 ad17 5 (bc) ? v dd io5 v dd io5 v dd io5 ? ? ta b le 68. 416-pin bgam pinout bm416 v dd io bank vref group i/o or4e02 or4e04 additional function p air
120 lattice semiconductor data sheet november, 2002 orca series 4 fpgas af19 5 (bc) 5 io pb20c pb27c ? l11t_a0 af20 5 (bc) 5 io pb20d pb27d ? l11c_a0 a c18 5 (bc) 6 io pb21a pb28c ? l12t_a0 a c17 5 (bc) 6 io pb21b pb28d vref_5_06 l12c_a0 r13 ? ? v dd 15 v dd 15 v dd 15 ? ? ad18 4 (br) 1 io pb22a pb30c ? l1t_d0 ae19 4 (br) 1 io pb22b pb30d ? l1c_d0 p13 ? ? vss vss vss ? ? ae20 4 (br) 1 io pb22c pb31c vref_4_01 l2t_d0 ad19 4 (br) 1 io pb22d pb31d ? l2c_d0 af21 4 (br) 1 io pb23a pb32c ? l3t_a0 ae21 4 (br) 1 io pb23b pb32d ? l3c_a0 ad20 4 (br) ? v dd io4 v dd io4 v dd io4 ? ? a c19 4 (br) 2 io pb23c pb33c ? l4t_a0 a c20 4 (br) 2 io pb23d pb33d vref_4_02 l4c_a0 af22 4 (br) 2 io pb24a pb34a ? ? p14 ? ? vss vss vss ? ? ae22 4 (br) 2 io pb24c pb34c ? ? ad21 4 (br) 3 io pb25a pb35a ? ? af23 4 (br) ? v dd io4 v dd io4 v dd io4 ? ? ae23 4 (br) 3 io pb25c pb35c ? l5t_d0 af24 4 (br) 3 io pb25d pb35d vref_4_03 l5c_d0 r10 ? ? vss vss vss ? ? a c21 4 (br) 3 io pb26c pb36c ? l6t_d0 ad22 4 (br) 3 io pb26d pb36d ? l6c_d0 ad23 4 (br) 4 io pb27a pb37a ? l7t_d0 ae24 4 (br) 4 io pb27b pb37b vref_4_04 l7c_d0 r11 ? ? vss vss vss ? ? a c22 4 (br) 4 io pb27c pb37c pll_ck5t/ppll l8t_a0 a c23 4 (br) 4 io pb27d pb37d pll_ck5c/ppll l8c_a0 p10 ? ? v dd 15 v dd 15 v dd 15 ? ? ad24 ? ? v dd 33 v dd 33 v dd 33 ? ? r12 ? ? vss vss vss ? ? r15 ? ? vss vss vss ? ? p11 ? ? v dd 15 v dd 15 v dd 15 ? ? ae25 ? ? v dd 33 v dd 33 v dd 33 ? ? a c24 4 (br) ? v dd io4 v dd io4 v dd io4 ? ? ad25 4 (br) 5 io pr26a pr38a pll_ck4t/pll2 l9t_a0 ad26 4 (br) 5 io pr26b pr38b pll_ck4c/pll2 l9c_a0 ab23 4 (br) 5 io pr25a pr37a vref_4_05 l10t_a0 aa23 4 (br) 5 io pr25b pr37b ? l10c_a0 a c25 4 (br) 6 io pr25c pr36a ? l11t_d0 ab24 4 (br) 6 io pr25d pr36b ? l11c_d0 ab25 4 (br) 6 io pr24a pr36c ? ? ta b le 68. 416-pin bgam pinout bm416 v dd io bank vref group i/o or4e02 or4e04 additional function p air
lattice semiconductor 121 data sheet november, 2002 orca series 4 fpgas aa24 4 (br) ? v dd io4 v dd io4 v dd io4 ? ? a c26 4 (br) 6 io pr24c pr35c vref_4_06 l12t_a0 ab26 4 (br) 6 io pr24d pr35d ? l12c_a0 y24 4 (br) 7 io pr23a pr34c ? l13t_d0 w23 4 (br) 7 io pr23b pr34d ? l13c_d0 aa25 4 (br) 7 io pr23c pr33c ? l14t_a0 aa26 4 (br) 7 io pr23d pr33d vref_4_07 l14c_a0 y23 4 (br) 7 io pr22a pr32c ? l15t_d0 w24 4 (br) 7 io pr22b pr32d ? l15c_d0 p12 ? ? v dd 15 v dd 15 v dd 15 ? ? y25 4 (br) 8 io pr22c pr31c ? l16t_a0 y26 4 (br) 8 io pr22d pr31d vref_4_08 l16c_a0 w25 4 (br) 8 io pr21c pr30c ? l17t_d0 v24 4 (br) 8 io pr21d pr30d ? l17c_d0 w26 3 (cr) ? v dd io3 v dd io3 v dd io3 ? ? v23 3 (cr) 1 io pr20c pr29c ? l1t_a0 u23 3 (cr) 1 io pr20d pr29d ? l1c_a0 m12 ? ? vss vss vss ? ? v25 3 (cr) 1 io pr19c pr28c vref_3_01 l2t_d0 u24 3 (cr) 1 io pr19d pr28d ? l2c_d0 v26 3 (cr) 2 io pr18a pr27a ? ? u26 3 (cr) ? v dd io3 v dd io3 v dd io3 ? ? u25 3 (cr) 2 io pr18c pr26a ? l3t_d0 t24 3 (cr) 2 io pr18d pr26b vref_3_02 l3c_d0 r23 3 (cr) 2 io pr17a pr25a ? l4t_a0 t23 3 (cr) 2 io pr17b pr25b ? l4c_a0 m15 ? ? vss vss vss ? ? t25 3 (cr) 3 io pr17c pr25c ? l5t_a0 t26 3 (cr) 3 io pr17d pr25d vref_3_03 l5c_a0 n15 ? ? v dd 15 v dd 15 v dd 15 ? ? r24 3 (cr) 4 io pr16c pr23c prck1t l6t_a0 r25 3 (cr) 4 io pr16d pr23d prck1c l6c_a0 r26 3 (cr) 4 io pr15a pr22c ? l7t_d0 p25 3 (cr) 4 io pr15b pr22d vref_3_04 l7c_d0 p24 3 (cr) ? v dd io3 v dd io3 v dd io3 ? ? p26 3 (cr) 5 io pr15c pr21c ? l8t_a0 n26 3 (cr) 5 io pr15d pr21d ? l8c_a0 m16 ? ? vss vss vss ? ? n23 3 (cr) 5 io pr14a pr20c prck0t l9t_a0 p23 3 (cr) 5 io pr14b pr20d prck0c l9c_a0 n16 ? ? v dd 15 v dd 15 v dd 15 ? ? n25 3 (cr) 5 io pr14c pr19c vref_3_05 l10t_a0 n24 3 (cr) 5 io pr14d pr19d ? l10c_a0 m26 3 (cr) 5 io pr13a pr18c ? l11t_a0 ta b le 68. 416-pin bgam pinout bm416 v dd io bank vref group i/o or4e02 or4e04 additional function p air
122 lattice semiconductor data sheet november, 2002 orca series 4 fpgas m25 3 (cr) 5 io pr13b pr18d ? l11c_a0 m17 ? ? vss vss vss ? ? m24 3 (cr) 6 io pr13c pr17c ? l12t_a0 m23 3 (cr) 6 io pr13d pr17d vref_3_06 l12c_a0 l26 3 (cr) 6 io pr12a pr16c ? l13t_a0 l25 3 (cr) 6 io pr12b pr16d ? l13c_a0 k26 3 (cr) ? v dd io3 v dd io3 v dd io3 ? ? l23 3 (cr) 7 io pr12c pr15a ? l14t_a0 l24 3 (cr) 7 io pr12d pr15b ? l14c_a0 k25 3 (cr) 7 io pr11a pr14a ? l15t_d0 j26 3 (cr) 7 io pr11b pr14b ? l15c_d0 n13 ? ? vss vss vss ? ? j25 3 (cr) 7 io pr11c pr14c vref_3_07 l16t_d0 k24 3 (cr) 7 io pr11d pr14d ? l16c_d0 h26 3 (cr) 8 io pr10c pr13c ? l17t_a0 g26 3 (cr) 8 io pr10d pr13d ? l17c_a0 n14 ? ? vss vss vss ? ? k23 3 (cr) 8 io pr9c pr12c vref_3_08 l18t_a0 j23 3 (cr) 8 io pr9d pr12d ? l18c_a0 m14 ? ? v dd 15 v dd 15 v dd 15 ? ? j24 2 (tr) 1 io pr8c pr11c ? l1t_d0 h25 2 (tr) 1 io pr8d pr11d vref_2_01 l1c_d0 g25 2 (tr) 1 io pr7a pr10c ? l2t_d0 h24 2 (tr) 1 io pr7b pr10d ? l2c_d0 l12 ? ? vss vss vss ? ? f26 2 (tr) 1 io pr7c pr9c ? l3t_a0 e26 2 (tr) 1 io pr7d pr9d ? l3c_a0 h23 2 (tr) 2 io pr6a pr7a ? l4t_d0 g24 2 (tr) 2 io pr6b pr7b ? l4c_d0 g23 2 (tr) ? v dd io2 v dd io2 v dd io2 ? ? f25 2 (tr) 2 io pr6c pr6a vref_2_02 l5t_a0 e25 2 (tr) 2 io pr6d pr6b ? l5c_a0 f24 2 (tr) 2 io pr5a pr6c ? ? l15 ? ? vss vss vss ? ? d26 2 (tr) 3 io pr5c pr5a ? l6t_a0 d25 2 (tr) 3 io pr5d pr5b vref_2_03 l6c_a0 c25 2 (tr) 3 io pr4a pr4a ? l7t_d0 d24 2 (tr) 3 io pr4b pr4b ? l7c_d0 f23 2 (tr) 3 io pr4c pr4c ? l8t_d0 e24 2 (tr) 3 io pr4d pr4d ? l8c_d0 l16 ? ? vss vss vss ? ? c26 2 (tr) 4 io pr3c pr3c pll_ck3t/pll1 l9t_d0 b25 2 (tr) 4 io pr3d pr3d pll_ck3c/pll1 l9c_d0 e23 2 (tr) ? v dd io2 v dd io2 v dd io2 ? ? ta b le 68. 416-pin bgam pinout bm416 v dd io bank vref group i/o or4e02 or4e04 additional function p air
lattice semiconductor 123 data sheet november, 2002 orca series 4 fpgas c24 ? ? v dd 33 v dd 33 v dd 33 ? ? n10 ? ? v dd 15 v dd 15 v dd 15 ? ? l17 ? ? vss vss vss ? ? m10 ? ? vss vss vss ? ? d23 ? ? v dd 33 v dd 33 v dd 33 ? ? n11 ? ? v dd 15 v dd 15 v dd 15 ? ? b24 ? ? io pll_vf pll_vf pll_vf ? d22 2 (tr) 5 io pt27d pt37d pll_ck2c/ppll l10c_d0 c23 2 (tr) 5 io pt27c pt37c pll_ck2t/ppll l10t_d0 m11 ? ? vss vss vss ? ? a24 2 (tr) 5 io pt26d pt36d vref_2_05 l11c_d0 b23 2 (tr) 5 io pt26c pt36c ? l11t_d0 c22 2 (tr) ? v dd io2 v dd io2 v dd io2 ? ? d21 2 (tr) 6 io pt26b pt35b ? l12c_a0 c21 2 (tr) 6 io pt26a pt35a ? l12t_a0 a23 2 (tr) 6 io pt25d pt34d vref_2_06 l13c_d0 b22 2 (tr) 6 io pt25c pt34c ? l13t_d0 a22 2 (tr) 7 io pt24d pt33d ? l14c_d0 b21 2 (tr) 7 io pt24c pt33c vref_2_07 l14t_d0 d20 2 (tr) ? v dd io2 v dd io2 v dd io2 ? ? d19 2 (tr) 7 io pt24b pt32d ? l15c_d0 c20 2 (tr) 7 io pt24a pt32c ? l15t_d0 b20 2 (tr) 8 io pt23d pt31d ? l16c_d0 c19 2 (tr) 8 io pt23c pt31c vref_2_08 l16t_d0 a21 2 (tr) 8 io pt22d pt29d ? l17c_a0 a20 2 (tr) 8 io pt22c pt29c ? l17t_a0 n12 ? ? v dd 15 v dd 15 v dd 15 ? ? b19 1 (tc) 1 io pt21d pt28d ? l1c_d0 c18 1 (tc) 1 io pt21c pt28c ? l1t_d0 k12 ? ? vss vss vss ? ? d18 1 (tc) 1 io pt20d pt27d vref_1_01 l2c_a0 d17 1 (tc) 1 io pt20c pt27c ? l2t_a0 a19 1 (tc) ? v dd io1 v dd io1 v dd io1 ? ? b18 1 (tc) 1 io pt20b pt27b ? l3c_d0 c17 1 (tc) 1 io pt20a pt27a ? l3t_d0 a18 1 (tc) 2 io pt19d pt26d ? l4c_d0 b17 1 (tc) 2 io pt19c pt26c vref_1_02 l4t_d0 k15 ? ? vss vss vss ? ? k16 ? ? vss vss vss ? ? a17 1 (tc) 2 io pt18d pt25d ? l5c_d0 b16 1 (tc) 2 io pt18c pt25c ? l5t_d0 d15 1 (tc) ? v dd io1 v dd io1 v dd io1 ? ? d16 1 (tc) 3 io pt18b pt24d ? l6c_a0 c16 1 (tc) 3 io pt18a pt24c vref_1_03 l6t_a0 ta b le 68. 416-pin bgam pinout bm416 v dd io bank vref group i/o or4e02 or4e04 additional function p air
124 lattice semiconductor data sheet november, 2002 orca series 4 fpgas a16 1 (tc) 3 io pt17d pt23d ? l7c_a0 a15 1 (tc) 3 io pt17c pt23c ? l7t_a0 k17 ? ? vss vss vss ? ? c15 1 (tc) 4 io pt16d pt21d ? l8c_a0 c14 1 (tc) 4 io pt16c pt21c ? l8t_a0 l13 ? ? v dd 15 v dd 15 v dd 15 ? ? b14 1 (tc) 4 io pt15d pt19d ? l9c_a0 a14 1 (tc) 4 io pt15c pt19c vref_1_04 l9t_a0 d14 1 (tc) ? v dd io1 v dd io1 v dd io1 ? ? d13 1 (tc) 5 io pt14d pt18d ptck1c l10c_a0 c13 1 (tc) 5 io pt14c pt18c ptck1t l10t_a0 l10 ? ? vss vss vss ? ? b13 1 (tc) 5 io pt13d pt17d ptck0c l11c_a0 a13 1 (tc) 5 io pt13c pt17c ptck0t l11t_a0 l14 ? ? v dd 15 v dd 15 v dd 15 ? ? a12 1 (tc) 5 io pt13b pt16d vref_1_05 l12c_a0 b12 1 (tc) 5 io pt13a pt16c ? l12t_a0 c12 1 (tc) 6 io pt12d pt15d ? l13c_a0 d12 1 (tc) 6 io pt12c pt15c ? l13t_a0 l11 ? ? vss vss vss ? ? b11 1 (tc) 6 io pt12b pt14d ? l14c_a0 a11 1 (tc) 6 io pt12a pt14c vref_1_06 l14t_a0 d11 0 (tl) 1 io pt11d pt13d mpi_rtry_n l1c_a0 c11 0 (tl) 1 io pt11c pt13c mpi_ack_n l1t_a0 a10 0 (tl) ? v dd io0 v dd io0 v dd io0 ? ? c10 0 (tl) 1 io pt11a pt13a vref_0_01 ? b10 0 (tl) 1 io pt10d pt12d m0 l2c_d0 a9 0 (tl) 1 io pt10c pt12c m1 l2t_d0 b9 0 (tl) 2 io pt10b pt12b mpi_clk l3c_a0 c9 0 (tl) 2 io pt10a pt12a a21/ mpi_burst_n l3t_a0 d10 0 (tl) 2 io pt9d pt11d m2 l4c_a0 d9 0 (tl) 2 io pt9c pt11c m3 l4t_a0 a8 0 (tl) 2 io pt9b pt11b vref_0_02 l5c_a0 b8 0 (tl) 2 io pt9a pt11a mpi_tea_n l5t_a0 k13 ? ? v dd 15 v dd 15 v dd 15 ? ? a7 0 (tl) 3 io pt8b pt9d vref_0_03 l6c_a0 a6 0 (tl) 3 io pt8a pt9c ? l6t_a0 c8 0 (tl) 3 io pt7d pt8d d0 l7c_d0 b7 0 (tl) 3 io pt7c pt8c tms l7t_d0 c7 0 (tl) 4 io pt7b pt7d a20/mpi_bdip_n l8c_d0 b6 0 (tl) 4 io pt7a pt7c a19/mpi_tsz1 l8t_d0 d7 0 (tl) 4 io pt6d pt6d a18/mpi_tsz0 l9c_a0 d8 0 (tl) 4 io pt6c pt6c d3 l9t_a0 ta b le 68. 416-pin bgam pinout bm416 v dd io bank vref group i/o or4e02 or4e04 additional function p air
lattice semiconductor 125 data sheet november, 2002 orca series 4 fpgas a5 0 (tl) ? v dd io0 v dd io0 v dd io0 ? ? c6 0 (tl) 5 io pt5d pt5d d1 l10c_d0 b5 0 (tl) 5 io pt5c pt5c d2 l10t_d0 b26 ? ? vss vss vss ? ? a4 0 (tl) 5 io pt4d pt4d tdi l11c_d1 c5 0 (tl) 5 io pt4c pt4c tck l11t_d1 b3 0 (tl) 6 io pt3d pt3d ? l12c_a0 a3 0 (tl) 6 io pt3c pt3c vref_0_06 l12t_a0 k10 ? ? vss vss vss ? ? d5 0 (tl) 6 io pt2d pt2d pll_ck1c/ppll l13c_a0 d6 0 (tl) 6 io pt2c pt2c pll_ck1t/ppll l13t_a0 b4 ? ? o pcfg_mpi_ irq pcfg_mpi_ir q cfg_irq_n/ mpi_irq_n ? b2 ? ? io pcclk pcclk cclk ? k14 ? ? v dd 15 v dd 15 v dd 15 ? ? c4 ? ? io pdone pdone done ? c3 ? ? v dd 33 v dd 33 v dd 33 ? ? k11 ? ? vss vss vss ? ? b15 1 (tc) ? v dd io1 v dd io1 v dd io1 ? ? af16 5 (bc) ? v dd io5 v dd io5 v dd io5 ? ? t12 ? ? vss vss vss ? ? t15 ? ? vss vss vss ? ? u13 ? ? v dd 15 v dd 15 v dd 15 ? ? p15 ? ? v dd 15 v dd 15 v dd 15 ? ? n17 ? ? v dd 15 v dd 15 v dd 15 ? ? m13 ? ? v dd 15 v dd 15 v dd 15 ? ? ta b le 68. 416-pin bgam pinout bm416 v dd io bank vref group i/o or4e02 or4e04 additional function p air
126 lattice semiconductor data sheet november, 2002 orca series 4 fpgas 680-pin pbgam pinout ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air a1 ? ? vss vss vss vss ? ? f5 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? e4 ? ? o prd_data prd_data prd_data rd_data/tdo ? e3 ? ? i preset_n preset_n preset_n reset_n ? d2 ? ? i prd_cfg_ n prd_cfg_ n prd_cfg_ n rd_cfg_n ? g5 ? ? i pprgrm_n pprgrm_n pprgrm_n prgrm_n ? d3 0 (tl) ? v dd io0 v dd io0 v dd io0 v dd io0 ? ? d1 0 (tl) 7 io pl2d pl2d pl2d pll_ck0c/hppll l21c_d2 f4 0 (tl) 7 io pl2c pl2c pl2c pll_ck0t/hppll l21t_d2 a2 ? ? vss vss vss vss ? ? f3 0 (tl) 7 io pl2b pl3d pl3d ? l22c_d0 g4 0 (tl) 7 io pl2a pl3c pl3c vref_0_07 l22t_d0 e2 0 (tl) 7 io pl3d pl4d pl4d d5 l23c_d2 h5 0 (tl) 7 io pl3c pl4c pl4c d6 l23t_d2 e5 0 (tl) ? v dd io0 v dd io0 v dd io0 v dd io0 ? ? e1 0 (tl) 8 io pl3b pl4b pl5d ? l24c_d0 f2 0 (tl) 8 io pl3a pl4a pl5c vref_0_08 l24t_d0 j5 0 (tl) 8 io pl4d pl5d pl6d hdc l25c_d3 f1 0 (tl) 8 io pl4c pl5c pl6c ldc_n l25t_d3 a18 ? ? vss vss vss vss ? ? h4 0 (tl) 8 io pl4b pl5b pl7d ? l26c_d0 g3 0 (tl) 8 io pl4a pl5a pl7c ? l26t_d0 h3 0 (tl) 9 io pl5d pl6d pl8d testcfg l27c_d0 g2 0 (tl) 9 io pl5c pl6c pl8c d7 l27t_d0 k5 0 (tl) 9 io pl5b pl7d pl9d vref_0_09 l28c_d3 g1 0 (tl) 9 io pl5a pl7c pl9c a17/ppc_a31 l28t_d3 j4 0 (tl) 9 io pl6d pl8d pl10d cs0_n l29c_d1 l5 0 (tl) 9 io pl6c pl8c pl10c cs1 l29t_d1 a33 ? ? vss vss vss vss ? ? j3 0 (tl) 10 io pl6b pl9d pl11d ? l30c_d0 h2 0 (tl) 10 io pl6a pl9c pl11c ? l30t_d0 h1 0 (tl) 10 io pl7d pl10d pl12d init_n l31c_d0 j2 0 (tl) 10 io pl7c pl10c pl12c dout l31t_d0 j1 0 (tl) 10 io pl7b pl11d pl13d vref_0_10 l32c_d1 k3 0 (tl) 10 io pl7a pl11c pl13c a16/ppc_a30 l32t_d1 l4 7 (cl) 1 io pl8d pl12d pl14d a15/ppc_a29 l1c_d1 k2 7 (cl) 1 io pl8c pl12c pl14c a14/ppc_a28 l1t_d1 l1 7 (cl) ? v dd io7 v dd io7 v dd io7 v dd io7 ? ? k1 7 (cl) 1 io pl8b pl12b pl15d ? l2c_d0 l2 7 (cl) 1 io pl8a pl12a pl15c ? l2t_d0 l3 7 (cl) 1 io pl9d pl13d pl16d vref_7_01 l3c_d1 n5 7 (cl) 1 io pl9c pl13c pl16c d4 l3t_d1
lattice semiconductor 127 data sheet november, 2002 orca series 4 fpgas am22 ? ? vss vss vss vss ? ? m4 7 (cl) 2 io pl9b pl13b pl17d ? l4c_a1 m2 7 (cl) 2 io pl9a pl13a pl17c ? l4t_a1 p5 7 (cl) 2 io pl10d pl14d pl18d rdy/busy_n/rclk l5c_d3 m1 7 (cl) 2 io pl10c pl14c pl18c vref_7_02 l5t_d3 m3 7 (cl) ? v dd io7 v dd io7 v dd io7 v dd io7 ? ? n1 7 (cl) 2 io pl10b pl15d pl19d a13/ppc_a27 l6c_a2 n4 7 (cl) 2 io pl10a pl15c pl19c a12/ppc_a26 l6t_a2 n2 7 (cl) 3 io pl11d pl16d pl20d ? l7c_d0 p1 7 (cl) 3 io pl11c pl16c pl20c ? l7t_d0 am32 ? ? vss vss vss vss ? ? p2 7 (cl) 3 io pl11b pl17d pl21d a11/ppc_a25 l8c_a0 p3 7 (cl) 3 io pl11a pl17c pl21c vref_7_03 l8t_a0 p4 7 (cl) 3 io pl12d pl18d pl22d ? l9c_d2 r1 7 (cl) 3 io pl12c pl18c pl22c ? l9t_d2 r4 7 (cl) 3 io pl12b pl18b pl22b ? l10c_a1 r2 7 (cl) 3 io pl12a pl18a pl22a ? l10t_a1 u5 7 (cl) 4 io pl13d pl19d pl23d rd_n/mpi_strb_n l11c_d0 t4 7 (cl) 4 io pl13c pl19c pl23c vref_7_04 l11t_d0 an1 ? ? vss vss vss vss ? ? v5 7 (cl) 4 io pl13b pl19b pl23b ? l12c_d3 t1 7 (cl) 4 io pl13a pl19a pl23a ? l12t_d3 t2 7 (cl) 4 io pl14d pl20d pl24d plck0c l13c_a0 t3 7 (cl) 4 io pl14c pl20c pl24c plck0t l13t_a0 r3 7 (cl) ? v dd io7 v dd io7 v dd io7 v dd io7 ? ? u4 7 (cl) 4 io pl14b pl20b pl24b ? l14c_a0 u3 7 (cl) 4 io pl14a pl20a pl24a ? l14t_a0 an2 ? ? vss vss vss vss ? ? u2 7 (cl) 5 io pl15d pl21d pl25d a10/ppc_a24 l15c_a0 v2 7 (cl) 5 io pl15c pl21c pl25c a9/ppc_a23 l15t_a0 an33 ? ? vss vss vss vss ? ? v3 7 (cl) 5 io pl15b pl21b pl25b ? l16c_a0 v4 7 (cl) 5 io pl15a pl21a pl25a ? l16t_a0 w5 7 (cl) 5 io pl16d pl22d pl26d a8/ppc_a22 l17c_a2 w2 7 (cl) 5 io pl16c pl22c pl26c vref_7_05 l17t_a2 w3 7 (cl) 5 io pl16b pl23d pl27d ? l18c_d1 y1 7 (cl) 5 io pl16a pl23c pl27c ? l18t_d1 w4 7 (cl) 6 io pl17d pl24d pl28d plck1c l19c_d2 aa1 7 (cl) 6 io pl17c pl24c pl28c plck1t l19t_d2 an34 ? ? vss vss vss vss ? ? y5 7 (cl) 6 io pl17b pl25d pl29d vref_7_06 l20c_a0 y4 7 (cl) 6 io pl17a pl25c pl29c a7/ppc_a21 l20t_a0 aa5 7 (cl) 6 io pl18d pl26d pl30d a6/ppc_a20 l21c_d3 ab1 7 (cl) 6 io pl18c pl26c pl30c a5/ppc_a19 l21t_d3 ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
128 lattice semiconductor data sheet november, 2002 orca series 4 fpgas u1 7 (cl) ? v dd io7 v dd io7 v dd io7 v dd io7 ? ? ab2 7 (cl) 7 io pl18b pl26b pl31d ? ? aa4 7 (cl) 7 io pl19d pl27d pl32d wr_n/mpi_rw l22c_a0 ab4 7 (cl) 7 io pl19c pl27c pl32c vref_7_07 l22t_a0 ab5 7 (cl) 7 io pl19b pl27b pl33d ? l23c_d3 ac 17 (cl) 7 io pl19a pl27a pl33c ? l23t_d3 ac 27 (cl) 8 io pl20d pl28d pl34d a4/ppc_a18 l23c_a2 ac 57 (cl) 8 io pl20c pl28c pl34c vref_7_08 l23t_a2 w1 7 (cl) ? v dd io7 v dd io7 v dd io7 v dd io7 ? ? ad2 7 (cl) 8 io pl20b pl29d pl35d a3/ppc_a17 l23c_a0 ad3 7 (cl) 8 io pl20a pl29c pl35c a2/ppc_a16 l23t_a0 ae1 7 (cl) 8 io pl21d pl30d pl36d a1/ppc_a15 l24c_a0 ae2 7 (cl) 8 io pl21c pl30c pl36c a0/ppc_a14 l24t_a0 ad4 7 (cl) 8 io pl21b pl31d pl37d dp0 l25c_d0 ae3 7 (cl) 8 io pl21a pl31c pl37c dp1 l25t_d0 af1 6 (bl) 1 io pl22d pl32d pl38d d8 l1c_a0 af2 6 (bl) 1 io pl22c pl32c pl38c vref_6_01 l1t_a0 ab13 ? ? vss vss vss vss ? ? af3 6 (bl) 1 io pl22b pl33d pl39d d9 l2c_a0 af4 6 (bl) 1 io pl22a pl33c pl39c d10 l2t_a0 ae5 6 (bl) 2 io pl23d pl34d pl40d ? l3c_d3 ag 16 (bl) 2 io pl23c pl34c pl40c vref_6_02 l3t_d3 ak5 6 (bl) ? v dd io6 v dd io6 v dd io6 v dd io6 ? ? ag 26 (bl) 2 io pl23b pl34b pl41d ? l4c_d2 af5 6 (bl) 2 io pl23a pl34a pl41c ? l4t_d2 ag 36 (bl) 3 io pl24d pl35b pl42d d11 l5c_a0 ag 46 (bl) 3 io pl24c pl35a pl42c d12 l5t_a0 ab14 ? ? vss vss vss vss ? ? ah1 6 (bl) 3 io pl24b pl36d pl43d ? l6c_a1 ah3 6 (bl) 3 io pl24a pl36c pl43c ? l6t_a1 ah4 6 (bl) 3 io pl25d pl36b pl44d vref_6_03 l7c_d0 ag 56 (bl) 3 io pl25c pl36a pl44c d13 l7t_d0 al3 6 (bl) ? v dd io6 v dd io6 v dd io6 v dd io6 ? ? ah2 6 (bl) 4 io pl25b pl37d pl44b ? ? aj3 6 (bl) 4 io pl25a pl38c pl45a ? ? aj2 6 (bl) 4 io pl26d pl37b pl45d ? l8c_d2 ah5 6 (bl) 4 io pl26c pl37a pl45c vref_6_04 l8t_d2 ab15 ? ? vss vss vss vss ? ? aj4 6 (bl) 4 io pl26b pl38b pl46d ? ? aj1 6 (bl) 4 io pl26a pl38a pl46a ? ? ak1 6 (bl) 4 io pl27d pl39d pl47d pll_ck7c/hppll l9c_a0 ak2 6 (bl) 4 io pl27c pl39c pl47c pll_ck7t/hppll l9t_a0 ab20 ? ? vss vss vss vss ? ? aj5 6 (bl) 4 io pl27b pl39b pl47b ? l10c_d1 ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
lattice semiconductor 129 data sheet november, 2002 orca series 4 fpgas ak3 6 (bl) 4 io pl27a pl39a pl47a ? l10t_d1 ab21 ? ? vss vss vss vss ? ? ak4 ? ? i ptemp ptemp ptemp ptemp ? am1 6 (bl) ? v dd io6 v dd io6 v dd io6 v dd io6 ? ? al1 ? ? io lvds_r lvds_r lvds_r lvds_r ? al2 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? ab22 ? ? vss vss vss vss ? ? ak6 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? al5 6 (bl) 5 io pb2a pb2a pb2a dp2 l11t_a0 am5 6 (bl) 5 io pb2b pb2b pb2b ? l11c_a0 am2 6 (bl) ? v dd io6 v dd io6 v dd io6 v dd io6 ? ? an4 6 (bl) 5 io pb2c pb2c pb2c pll_ck6t/ppll l12t_d2 ak7 6 (bl) 5 io pb2d pb2d pb2d pll_ck6c/ppll l12c_d2 al6 6 (bl) 5 io pb3a pb3c pb3c ? l13t_a0 am6 6 (bl) 5 io pb3b pb3d pb3d ? l13c_a0 al7 6 (bl) 5 io pb3c pb4a pb4c vref_6_05 l14t_d1 an5 6 (bl) 5 io pb3d pb4b pb4d dp3 l14c_d1 ak8 6 (bl) 6 io pb4a pb4c pb5c ? l15t_d3 ap5 6 (bl) 6 io pb4b pb4d pb5d ? l15c_d3 ab32 ? ? vss vss vss vss ? ? an6 6 (bl) 6 io pb4c pb5c pb6c vref_6_06 l16t_d2 ak9 6 (bl) 6 io pb4d pb5d pb6d d14 l16c_d2 ap6 6 (bl) 6 io pb5a pb6a pb7c ? l17t_d2 al8 6 (bl) 6 io pb5b pb6b pb7d ? l17c_d2 am4 6 (bl) ? v dd io6 v dd io6 v dd io6 v dd io6 ? ? am7 6 (bl) 7 io pb5c pb6c pb8c d15 l18t_a0 am8 6 (bl) 7 io pb5d pb6d pb8d d16 l18c_a0 ak10 6 (bl) 7 io pb6a pb7c pb9c d17 l19t_d3 ap7 6 (bl) 7 io pb6b pb7d pb9d d18 l19c_d3 al4 ? ? vss vss vss vss ? ? ak11 6 (bl) 7 io pb6c pb8c pb10c vref_6_07 l20t_d1 am9 6 (bl) 7 io pb6d pb8d pb10d d19 l20c_d1 al10 6 (bl) 8 io pb7a pb9c pb11c d20 l21t_d2 ap8 6 (bl) 8 io pb7b pb9d pb11d d21 l21c_d2 ap9 6 (bl) 8 io pb7c pb10c pb12c vref_6_08 l22t_d1 am10 6 (bl) 8 io pb7d pb10d pb12d d22 l22c_d1 ak12 6 (bl) 9 io pb8a pb11a pb13a ? l23t_d0 al11 6 (bl) 9 io pb8b pb11b pb13b ? l23c_d0 al31 ? ? vss vss vss vss ? ? an10 6 (bl) 9 io pb8c pb11c pb13c d23 l24t_a0 ap10 6 (bl) 9 io pb8d pb11d pb13d d24 l24c_a0 an11 6 (bl) 9 io pb9a pb12a pb14a ? l25t_a0 am11 6 (bl) 9 io pb9b pb12b pb14b ? l25c_a0 an3 6 (bl) ? v dd io6 v dd io6 v dd io6 v dd io6 ? ? ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
130 lattice semiconductor data sheet november, 2002 orca series 4 fpgas ak13 6 (bl) 9 io pb9c pb12c pb14c vref_6_09 l26t_d0 al12 6 (bl) 9 io pb9d pb12d pb14d d25 l26c_d0 an12 6 (bl) 9 io pb10a pb13a pb15c ? l27t_d2 ak14 6 (bl) 9 io pb10b pb13b pb15d ? l27c_d2 am3 ? ? vss vss vss vss ? ? ap12 6 (bl) 10 io pb10c pb13c pb16c d26 l28t_a0 ap13 6 (bl) 10 io pb10d pb13d pb16d d27 l28c_a0 al13 6 (bl) 10 io pb11a pb14a pb17c ? l29t_a1 an13 6 (bl) 10 io pb11b pb14b pb17d ? l29c_a1 ap3 6 (bl) ? v dd io6 v dd io6 v dd io6 v dd io6 ? ? ap14 6 (bl) 10 io pb11c pb14c pb18c vref_6_10 l30t_d3 ak15 6 (bl) 10 io pb11d pb14d pb18d d28 l30c_d3 am14 6 (bl) 11 io pb12a pb15c pb19c d29 l31t_d1 ak16 6 (bl) 11 io pb12b pb15d pb19d d30 l31c_d1 am13 ? ? vss vss vss vss ? ? ap15 6 (bl) 11 io pb12c pb16c pb20c vref_6_11 l32t_a2 al15 6 (bl) 11 io pb12d pb16d pb20d d31 l32c_a2 an16 5 (bc) 1 io pb13a pb17c pb21c ? l1t_d2 ak17 5 (bc) 1 io pb13b pb17d pb21d ? l1c_d2 am16 5 (bc) 1 io pb13c pb18c pb22c vref_5_01 l2t_a1 ap16 5 (bc) 1 io pb13d pb18d pb22d ? l2c_a1 an17 5 (bc) 2 io pb14a pb19a pb23a ? l3t_a1 al17 5 (bc) 2 io pb14b pb19b pb23b ? l3c_a1 y15 ? ? vss vss vss vss ? ? am17 5 (bc) 2 io pb14c pb19c pb23c pbck0t l4t_a0 am18 5 (bc) 2 io pb14d pb19d pb23d pbck0c l4c_a0 al18 5 (bc) 2 io pb15a pb20a pb24a ? l5t_a1 an18 5 (bc) 2 io pb15b pb20b pb24b ? l5c_a1 am12 5 (bc) ? v dd io5 v dd io5 v dd io5 v dd io5 ? ? al19 5 (bc) 2 io pb15c pb20c pb24c vref_5_02 l6t_d0 ak18 5 (bc) 2 io pb15d pb20d pb24d ? l6c_d0 am19 5 (bc) 2 io pb16a pb21a pb25c ? l7t_a0 an19 5 (bc) 2 io pb16b pb21b pb25d ? l7c_a0 ap20 5 (bc) 3 io pb16c pb21c pb26c ? l8t_a0 an20 5 (bc) 3 io pb16d pb21d pb26d vref_5_03 l8c_a0 ap21 5 (bc) 3 io pb17a pb22c pb27c ? l9t_a0 an21 5 (bc) 3 io pb17b pb22d pb27d ? l9c_a0 y20 ? ? vss vss vss vss ? ? am21 5 (bc) 3 io pb17c pb23c pb28c pbck1t l10t_a0 al21 5 (bc) 3 io pb17d pb23d pb28d pbck1c l10c_a0 ap22 5 (bc) 4 io pb18a pb24c pb29c ? l11t_a0 an22 5 (bc) 4 io pb18b pb24d pb29d ? l11c_a0 am15 5 (bc) ? v dd io5 v dd io5 v dd io5 v dd io5 ? ? al22 5 (bc) 4 io pb18c pb25c pb30c ? l12t_a0 ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
lattice semiconductor 131 data sheet november, 2002 orca series 4 fpgas al23 5 (bc) 4 io pb18d pb25d pb30d vref_5_04 l12c_a0 y21 ? ? vss vss vss vss ? ? ak22 5 (bc) 4 io pb19a pb26a pb31c ? l13t_d2 an23 5 (bc) 4 io pb19b pb26b pb31d ? l13c_d2 y22 ? ? vss vss vss vss ? ? ap23 5 (bc) 5 io pb19c pb26c pb32c ? l14t_a3 ak23 5 (bc) 5 io pb19d pb26d pb32d vref_5_05 l14c_a3 an24 5 (bc) 5 io pb20a pb27a pb33c ? l15t_a0 am24 5 (bc) 5 io pb20b pb27b pb33d ? l15c_a0 am20 5 (bc) ? v dd io5 v dd io5 v dd io5 v dd io5 ? ? al24 5 (bc) 5 io pb20c pb27c pb34c ? l16t_d2 ap25 5 (bc) 5 io pb20d pb27d pb34d ? l16t_d2 ak24 5 (bc) 6 io pb21a pb28c pb35c ? l17t_d3 ap26 5 (bc) 6 io pb21b pb28d pb35d vref_5_06 l17c_d3 al25 5 (bc) 6 io pb21c pb29c pb36c ? l18t_a0 am25 5 (bc) 6 io pb21d pb29d pb36d ? l18c_a0 ap27 4 (br) 1 io pb22a pb30c pb37c ? l1t_a0 an27 4 (br) 1 io pb22b pb30d pb37d ? l1c_a0 v16 ? ? vss vss vss vss ? ? ak25 4 (br) 1 io pb22c pb31c pb38c vref_4_01 l2t_d0 al26 4 (br) 1 io pb22d pb31d pb38d ? l2c_d0 am27 4 (br) 1 io pb23a pb32c pb39c ? l3t_d1 ak26 4 (br) 1 io pb23b pb32d pb39d ? l3c_d1 ak30 4 (br) ? v dd io4 v dd io4 v dd io4 v dd io4 ? ? ap28 4 (br) 2 io pb23c pb33c pb40c ? l4t_a0 an28 4 (br) 2 io pb23d pb33d pb40d vref_4_02 l4c_a0 al27 4 (br) 2 io pb24a pb34a pb41c ? l5t_a0 al28 4 (br) 2 io pb24b pb34b pb41d ? l5c_a0 v17 ? ? vss vss vss vss ? ? ak27 4 (br) 2 io pb24c pb34c pb42c ? ? am28 4 (br) 3 io pb25a pb35a pb43a ? ? an29 4 (br) 3 io pb25b pb35b pb43d ? ? al32 4 (br) ? v dd io4 v dd io4 v dd io4 v dd io4 ? ? ak28 4 (br) 3 io pb25c pb35c pb44c ? l6t_d1 am29 4 (br) 3 io pb25d pb35d pb44d vref_4_03 l6c_d1 al29 4 (br) 3 io pb26a pb36a pb45a ? l7t_a2 ap29 4 (br) 3 io pb26b pb36b pb45b ? l7c_a2 v18 ? ? vss vss vss vss ? ? ap30 4 (br) 3 io pb26c pb36c pb45c ? l8t_a0 an30 4 (br) 3 io pb26d pb36d pb45d ? l8c_a0 ak29 4 (br) 4 io pb27a pb37a pb46c ? l9t_d1 am30 4 (br) 4 io pb27b pb37b pb46d vref_4_04 l9c_d1 v19 ? ? vss vss vss vss ? ? al30 4 (br) 4 io pb27c pb37c pb47c pll_ck5t/ppll l10t_d2 ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
132 lattice semiconductor data sheet november, 2002 orca series 4 fpgas ap31 4 (br) 4 io pb27d pb37d pb47d pll_ck5c/ppll l10c_d2 an31 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? v34 ? ? vss vss vss vss ? ? w16 ? ? vss vss vss vss ? ? ak31 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? am31 4 (br) ? v dd io4 v dd io4 v dd io4 v dd io4 ? ? aj30 4 (br) 5 io pr26a pr38a pr46c pll_ck4t/pll2 l11t_d1 ak32 4 (br) 5 io pr26b pr38b pr46d pll_ck4c/pll2 l11c_d1 w17 ? ? vss vss vss vss ? ? al33 4 (br) 5 io pr26c pr38c pr45c ? l12t_d2 ah30 4 (br) 5 io pr26d pr38d pr45d ? l12c_d2 al34 4 (br) 5 io pr25a pr37a pr44c vref_4_05 l13t_d2 aj31 4 (br) 5 io pr25b pr37b pr44d ? l13c_d2 w18 ? ? vss vss vss vss ? ? aj32 4 (br) 6 io pr25c pr36a pr43c ? l14t_d0 ah31 4 (br) 6 io pr25d pr36b pr43d ? l14c_d0 ak33 4 (br) 6 io pr24a pr36c pr42c ? l15t_d2 a g30 4 (br) 6 io pr24b pr36d pr42d ? l15c_d2 am34 4 (br) ? v dd io4 v dd io4 v dd io4 v dd io4 ? ? ak34 4 (br) 6 io pr24c pr35c pr41c vref_4_06 l16t_d0 aj33 4 (br) 6 io pr24d pr35d pr41d ? l16c_d0 aj34 4 (br) 7 io pr23a pr34c pr40c ? l17t_d2 a g31 4 (br) 7 io pr23b pr34d pr40d ? l17c_d2 w19 ? ? vss vss vss vss ? ? a g32 4 (br) 7 io pr23c pr33c pr39c ? l18t_d0 ah33 4 (br) 7 io pr23d pr33d pr39d vref_4_07 l18c_d0 ah34 4 (br) 7 io pr22a pr32c pr38c ? l19t_d2 af31 4 (br) 7 io pr22b pr32d pr38d ? l19c_d2 a g33 4 (br) 8 io pr22c pr31c pr37c ? l20t_d1 ae31 4 (br) 8 io pr22d pr31d pr37d vref_4_08 l20c_d1 a g34 4 (br) 8 io pr21a pr30a pr36a ? l22t_d0 af33 4 (br) 8 io pr21b pr30b pr36b ? l22c_d0 y13 ? ? vss vss vss vss ? ? ad30 4 (br) 8 io pr21c pr30c pr36c ? l21t_d3 af34 4 (br) 8 io pr21d pr30d pr36d ? l21c_d3 ae32 3 (cr) 1 io pr20a pr29a pr35c ? l1t_d1 a c30 3 (cr) 1 io pr20b pr29b pr35d ? l1c_d1 l34 3 (cr) ? v dd io3 v dd io3 v dd io3 v dd io3 ? ? ae33 3 (cr) 1 io pr20c pr29c pr34c ? l2t_d1 a c31 3 (cr) 1 io pr20d pr29d pr34d ? l2c_d1 ad31 3 (cr) 1 io pr19a pr28a pr34a ? ? ae34 3 (cr) 1 io pr19b pr28b pr33b ? ? r21 ? ? vss vss vss vss ? ? ad32 3 (cr) 1 io pr19c pr28c pr33c vref_3_01 l3t_d1 ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
lattice semiconductor 133 data sheet november, 2002 orca series 4 fpgas ab30 3 (cr) 1 io pr19d pr28d pr33d ? l3c_d1 ab31 3 (cr) 2 io pr18a pr27a pr32c ? l4t_d0 aa30 3 (cr) 2 io pr18b pr27b pr32d ? l4c_d0 m32 3 (cr) ? v dd io3 v dd io3 v dd io3 v dd io3 ? ? a c33 3 (cr) 2 io pr18c pr26a pr31c ? l5t_a0 ab33 3 (cr) 2 io pr18d pr26b pr31d vref_3_02 l5c_a0 aa32 3 (cr) 2 io pr17a pr25a pr30c ? l6t_d1 y30 3 (cr) 2 io pr17b pr25b pr30d ? l6c_d1 r22 ? ? vss vss vss vss ? ? ab34 3 (cr) 3 io pr17c pr25c pr29c ? l7t_d3 w30 3 (cr) 3 io pr17d pr25d pr29d vref_3_03 l7c_d3 aa33 3 (cr) 3 io pr16a pr24c pr28c ? l8t_d1 w31 3 (cr) 3 io pr16b pr24d pr28d ? l8c_d1 y34 3 (cr) 4 io pr16c pr23c pr27c prck1t l9t_d0 w33 3 (cr) 4 io pr16d pr23d pr27d prck1c l9c_d0 v30 3 (cr) 4 io pr15a pr22c pr26c ? l10t_a0 v31 3 (cr) 4 io pr15b pr22d pr26d vref_3_04 l10c_a0 r32 3 (cr) ? v dd io3 v dd io3 v dd io3 v dd io3 ? ? v33 3 (cr) 5 io pr15c pr21c pr25c ? l11t_a0 v32 3 (cr) 5 io pr15d pr21d pr25d ? l11c_a0 t16 ? ? vss vss vss vss ? ? t34 3 (cr) 5 io pr14a pr20c pr24c prck0t l13t_d2 u31 3 (cr) 5 io pr14b pr20d pr24d prck0c l13c_d2 t32 3 (cr) 5 io pr14c pr19c pr23c vref_3_05 l14t_a0 t31 3 (cr) 5 io pr14d pr19d pr23d ? l14c_a0 r31 3 (cr) 5 io pr13a pr18c pr22c ? l15t_d1 r34 3 (cr) 5 io pr13b pr18d pr22d ? l15c_d1 t17 ? ? vss vss vss vss ? ? p34 3 (cr) 6 io pr13c pr17c pr21c ? l16t_a1 p32 3 (cr) 6 io pr13d pr17d pr21d vref_3_06 l16c_a1 p31 3 (cr) 6 io pr12a pr16c pr20c ? l17t_a1 p33 3 (cr) 6 io pr12b pr16d pr20d ? l17c_a1 u34 3 (cr) ? v dd io3 v dd io3 v dd io3 v dd io3 ? ? n33 3 (cr) 7 io pr12c pr15a pr19c ? l18t_a1 n31 3 (cr) 7 io pr12d pr15b pr19d ? l18c_a1 m31 3 (cr) 7 io pr11a pr14a pr18c ? l19t_a1 m33 3 (cr) 7 io pr11b pr14b pr18d ? l19c_a1 t18 ? ? vss vss vss vss ? ? m34 3 (cr) 7 io pr11c pr14c pr17c vref_3_07 l20t_d1 l32 3 (cr) 7 io pr11d pr14d pr17d ? l20c_d1 l33 3 (cr) 8 io pr10a pr13a pr15a ? ? l31 3 (cr) 8 io pr10b pr13b pr16d ? ? w34 3 (cr) ? v dd io3 v dd io3 v dd io3 v dd io3 ? ? k34 3 (cr) 8 io pr10c pr13c pr15c ? l21t_a0 ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
134 lattice semiconductor data sheet november, 2002 orca series 4 fpgas k33 3 (cr) 8 io pr10d pr13d pr15d ? l21c_a0 k32 3 (cr) 8 io pr9a pr12a pr14a ? ? t19 ? ? vss vss vss vss ? ? n30 3 (cr) 8 io pr9c pr12c pr14c vref_3_08 l22t_d2 k31 3 (cr) 8 io pr9d pr12d pr14d ? l22c_d2 h34 2 (tr) 1 io pr8a pr11a pr13a ? l1t_a0 j34 2 (tr) 1 io pr8b pr11b pr13b ? l1c_a0 j33 2 (tr) 1 io pr8c pr11c pr13c ? l2t_a1 j31 2 (tr) 1 io pr8d pr11d pr13d vref_2_01 l2c_a1 j32 2 (tr) 1 io pr7a pr10c pr12c ? l3t_d1 g34 2 (tr) 1 io pr7b pr10d pr12d ? l3c_d1 n32 ? ? vss vss vss vss ? ? h33 2 (tr) 1 io pr7c pr9c pr11c ? l4t_a0 h32 2 (tr) 1 io pr7d pr9d pr11d ? l4c_a0 h31 2 (tr) 2 io pr6a pr7a pr10c ? l5t_d1 g33 2 (tr) 2 io pr6b pr7b pr10d ? l5c_d1 a32 2 (tr) ? v dd io2 v dd io2 v dd io2 v dd io2 ? ? f33 2 (tr) 2 io pr6c pr6a pr9c vref_2_02 l6t_d0 g32 2 (tr) 2 io pr6d pr6b pr9d ? l6c_d0 k30 2 (tr) 2 io pr5a pr6c pr8c ? l7t_d2 g31 2 (tr) 2 io pr5b pr6d pr8d ? l7c_d2 p13 ? ? vss vss vss vss ? ? e34 2 (tr) 3 io pr5c pr5a pr7c ? l8t_d2 j30 2 (tr) 3 io pr5d pr5b pr7d vref_2_03 l8c_d2 f32 2 (tr) 3 io pr4a pr4a pr6c ? l9t_a0 f31 2 (tr) 3 io pr4b pr4b pr6d ? l9c_a0 b32 2 (tr) ? v dd io2 v dd io2 v dd io2 v dd io2 ? ? e33 2 (tr) 3 io pr4c pr4c pr5c ? l10t_a0 d33 2 (tr) 3 io pr4d pr4d pr5d ? l10c_a0 h30 2 (tr) 4 io pr3a pr3a pr4c ? l11t_d2 e32 2 (tr) 4 io pr3b pr3b pr4d vref_2_04 l11c_d2 p14 ? ? vss vss vss vss ? ? e31 2 (tr) 4 io pr3c pr3c pr3c pll_ck3t/pll1 l12t_a0 g30 2 (tr) 4 io pr3d pr3d pr3d pll_ck3c/pll1 l12c_a0 c31 2 (tr) ? v dd io2 v dd io2 v dd io2 v dd io2 ? ? f30 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? p15 ? ? vss vss vss vss ? ? p20 ? ? vss vss vss vss ? ? e29 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? d30 ? ? io pll_vf pll_vf pll_vf pll_vf ? c30 2 (tr) 5 io pt27d pt37d pt47d pll_ck2c/ppll l13c_d0 b31 2 (tr) 5 io pt27c pt37c pt47c pll_ck2t/ppll l13t_d0 p21 ? ? vss vss vss vss ? ? e28 2 (tr) 5 io pt27b pt37b pt46d ? l14c_d2 ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
lattice semiconductor 135 data sheet november, 2002 orca series 4 fpgas b30 2 (tr) 5 io pt27a pt37a pt46c ? l14t_d2 d29 2 (tr) 5 io pt26d pt36d pt45d vref_2_05 l15c_d2 a31 2 (tr) 5 io pt26c pt36c pt45c ? l15t_d2 c33 2 (tr) ? v dd io2 v dd io2 v dd io2 v dd io2 ? ? e27 2 (tr) 6 io pt26b pt35b pt43d ? l17c_d1 c29 2 (tr) 6 io pt26a pt35a pt43c ? l17t_d1 a30 2 (tr) 6 io pt25d pt34d pt42d vref_2_06 l18c_d3 e26 2 (tr) 6 io pt25c pt34c pt42c ? l18t_d3 p22 ? ? vss vss vss vss ? ? a29 2 (tr) 7 io pt25b pt34b pt41d ? l19c_d2 d27 2 (tr) 7 io pt25a pt34a pt41c ? l19t_d2 c28 2 (tr) 7 io pt24d pt33d pt40d ? l20c_a0 c27 2 (tr) 7 io pt24c pt33c pt40c vref_2_07 l20t_a0 c34 2 (tr) ? v dd io2 v dd io2 v dd io2 v dd io2 ? ? b28 2 (tr) 7 io pt24b pt32d pt39d ? l21c_d2 e25 2 (tr) 7 io pt24a pt32c pt39c ? l21t_d2 a28 2 (tr) 8 io pt23d pt31d pt38d ? l22c_d2 d26 2 (tr) 8 io pt23c pt31c pt38c vref_2_08 l22t_d2 r13 ? ? vss vss vss vss ? ? c26 2 (tr) 8 io pt23b pt30d pt37d ? ? b27 2 (tr) 8 io pt23a pt30a pt37a ? ? d25 2 (tr) 8 io pt22d pt29d pt36d ? l23c_d2 a27 2 (tr) 8 io pt22c pt29c pt36c ? l23t_d2 b26 2 (tr) 8 io pt22b pt29b pt36b ? l24c_a0 a26 2 (tr) 8 io pt22a pt29a pt36a ? l24t_a0 c25 1 (tc) 1 io pt21d pt28d pt35d ? l1c_d1 e24 1 (tc) 1 io pt21c pt28c pt35c ? l1t_d1 c22 ? ? vss vss vss vss ? ? a25 1 (tc) 1 io pt21b pt28b pt35b ? l2c_d2 d24 1 (tc) 1 io pt21a pt28a pt35a ? l2t_d2 d23 1 (tc) 1 io pt20d pt27d pt34d vref_1_01 l3c_d1 b25 1 (tc) 1 io pt20c pt27c pt34c ? l3t_d1 a11 1 (tc) ? v dd io1 v dd io1 v dd io1 v dd io1 ? ? c24 1 (tc) 1 io pt20b pt27b pt33d ? l4c_d1 e23 1 (tc) 1 io pt20a pt27a pt33c ? l4t_d1 b24 1 (tc) 2 io pt19d pt26d pt32d ? l5c_d1 d22 1 (tc) 2 io pt19c pt26c pt32c vref_1_02 l5t_d1 c32 ? ? vss vss vss vss ? ? e22 1 (tc) 2 io pt19b pt26b pt31d ? l6c_d0 d21 1 (tc) 2 io pt19a pt26a pt31c ? l6t_d0 d4 ? ? vss vss vss vss ? ? b23 1 (tc) 2 io pt18d pt25d pt30d ? l7c_a0 b22 1 (tc) 2 io pt18c pt25c pt30c ? l7t_a0 a17 1 (tc) ? v dd io1 v dd io1 v dd io1 v dd io1 ? ? ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
136 lattice semiconductor data sheet november, 2002 orca series 4 fpgas a23 1 (tc) 3 io pt18b pt24d pt29d ? l8c_d1 c21 1 (tc) 3 io pt18a pt24c pt29c vref_1_03 l8t_d1 d20 1 (tc) 3 io pt17d pt23d pt28d ? l9c_d2 a22 1 (tc) 3 io pt17c pt23c pt28c ? l9t_d2 d31 ? ? vss vss vss vss ? ? a21 1 (tc) 3 io pt17b pt22d pt27d ? l10c_a0 b21 1 (tc) 3 io pt17a pt22c pt27c ? l10t_a0 b20 1 (tc) 4 io pt16d pt21d pt26d ? l11c_a0 a20 1 (tc) 4 io pt16c pt21c pt26c ? l11t_a0 b19 1 (tc) 4 io pt16b pt20d pt25d ? l12c_a0 c19 1 (tc) 4 io pt16a pt20c pt25c ? l12t_a0 e19 1 (tc) 4 io pt15d pt19d pt24d ? l13c_d0 d18 1 (tc) 4 io pt15c pt19c pt24c vref_1_04 l13t_d0 a19 1 (tc) ? v dd io1 v dd io1 v dd io1 v dd io1 ? ? c18 1 (tc) 4 io pt15b pt19b pt24b ? l14c_a0 b18 1 (tc) 4 io pt15a pt19a pt24a ? l14t_a0 b17 1 (tc) 5 io pt14d pt18d pt23d ptck1c l15c_d0 c17 1 (tc) 5 io pt14c pt18c pt23c ptck1t l15t_d0 n3 ? ? vss vss vss vss ? ? a16 1 (tc) 5 io pt14b pt18b pt23b ? l16c_d2 d17 1 (tc) 5 io pt14a pt18a pt23a ? l16t_d2 b16 1 (tc) 5 io pt13d pt17d pt22d ptck0c l17c_a0 c16 1 (tc) 5 io pt13c pt17c pt22c ptck0t l17t_a0 e18 1 (tc) 5 io pt13b pt16d pt21d vref_1_05 l18c_d3 a15 1 (tc) 5 io pt13a pt16c pt21c ? l18t_d3 d15 1 (tc) 6 io pt12d pt15d pt20d ? l19c_d2 a14 1 (tc) 6 io pt12c pt15c pt20c ? l19t_d2 n13 ? ? vss vss vss vss ? ? e17 1 (tc) 6 io pt12b pt14d pt19d ? l20c_d3 a13 1 (tc) 6 io pt12a pt14c pt19c vref_1_06 l20t_d3 e16 0 (tl) 1 io pt11d pt13d pt18d mpi_rtry_n l1c_d1 d14 0 (tl) 1 io pt11c pt13c pt18c mpi_ack_n l1t_d1 a3 0 (tl) ? v dd io0 v dd io0 v dd io0 v dd io0 ? ? c14 0 (tl) 1 io pt11b pt13b pt17d ? l2c_d0 d13 0 (tl) 1 io pt11a pt13a pt17c vref_0_01 l2t_d0 a12 0 (tl) 1 io pt10d pt12d pt16d m0 l3c_a0 b12 0 (tl) 1 io pt10c pt12c pt16c m1 l3t_a0 a34 ? ? vss vss vss vss ? ? e15 0 (tl) 2 io pt10b pt12b pt15d mpi_clk l4c_d3 b11 0 (tl) 2 io pt10a pt12a pt15c a21/mpi_burst_n l4t_d3 c11 0 (tl) 2 io pt9d pt11d pt14d m2 l5c_d2 e14 0 (tl) 2 io pt9c pt11c pt14c m3 l5t_d2 b3 0 (tl) ? v dd io0 v dd io0 v dd io0 v dd io0 ? ? d12 0 (tl) 2 io pt9b pt11b pt13d vref_0_02 l6c_a0 ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
lattice semiconductor 137 data sheet november, 2002 orca series 4 fpgas d11 0 (tl) 2 io pt9a pt11a pt13c mpi_tea_n l6t_a0 a10 0 (tl) 3 io pt8d pt10d pt12d ? l7c_a0 b10 0 (tl) 3 io pt8c pt10c pt12c ? l7t_a0 c9 0 (tl) 3 io pt8b pt9d pt11d vref_0_03 l8c_d0 d10 0 (tl) 3 io pt8a pt9c pt11c ? l8t_d0 b9 0 (tl) 3 io pt7d pt8d pt10d d0 l9c_a0 a9 0 (tl) 3 io pt7c pt8c pt10c tms l9t_a0 b1 ? ? vss vss vss vss ? ? d9 0 (tl) 4 io pt7b pt7d pt9d a20/mpi_bdip_n l10c_d2 a8 0 (tl) 4 io pt7a pt7c pt9c a19/mpi_tsz1 l10t_d2 b8 0 (tl) 4 io pt6d pt6d pt8d a18/mpi_tsz0 l11c_d3 e12 0 (tl) 4 io pt6c pt6c pt8c d3 l11t_d3 c1 0 (tl) ? v dd io0 v dd io0 v dd io0 v dd io0 ? ? c8 0 (tl) 4 io pt6b pt6b pt7d vref_0_04 l12c_a0 d8 0 (tl) 4 io pt6a pt6a pt7c ? l12t_a0 e11 0 (tl) 5 io pt5d pt5d pt6d d1 l13c_d3 a7 0 (tl) 5 io pt5c pt5c pt6c d2 l13t_d3 b2 ? ? vss vss vss vss ? ? a6 0 (tl) 5 io pt5b pt5b pt5d ? l14c_d0 b7 0 (tl) 5 io pt5a pt5a pt5c vref_0_05 l14t_d0 c7 0 (tl) 5 io pt4d pt4d pt4d tdi l15c_a0 d7 0 (tl) 5 io pt4c pt4c pt4c tck l15t_a0 c2 0 (tl) ? v dd io0 v dd io0 v dd io0 v dd io0 ? ? e10 0 (tl) 5 io pt4b pt4b pt4b ? l16c_d4 a5 0 (tl) 5 io pt4a pt4a pt4a ? l16t_d4 b6 0 (tl) 6 io pt3d pt3d pt3d ? l17c_d2 e9 0 (tl) 6 io pt3c pt3c pt3c vref_0_06 l17t_d2 b33 ? ? vss vss vss vss ? ? a4 0 (tl) 6 io pt3b pt3b pt3b ? l18c_d0 b5 0 (tl) 6 io pt3a pt3a pt3a ? l18t_d0 d6 0 (tl) 6 io pt2d pt2d pt2d pll_ck1c/ppll l19c_a0 c6 0 (tl) 6 io pt2c pt2c pt2c pll_ck1t/ppll l19t_a0 c4 0 (tl) ? v dd io0 v dd io0 v dd io0 v dd io0 ? ? c5 0 (tl) 6 io pt2b pt2b pt2b ? l20c_d1 e8 0 (tl) 6 io pt2a pt2a pt2a ? l20t_d1 e7 ? ? o pcfg_mpi_ir q pcfg_mpi_ir q pcfg_mpi_ir q cfg_irq_n/ mpi_irq_n ? e6 ? ? io pcclk pcclk pcclk cclk ? b4 ? ? io pdone pdone pdone done ? d5 ? ? v dd 33 v dd 33 v dd 33 v dd 33 ? ? b34 ? ? vss vss vss vss ? ? a24 1 (tc) ? v dd io1 v dd io1 v dd io1 v dd io1 ? ? am23 5 (bc) ? v dd io5 v dd io5 v dd io5 v dd io5 ? ? ap1 ? ? vss vss vss vss ? ? k4 0 (tl) 10 io unused pl9a pl11a ? ? ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
138 lattice semiconductor data sheet november, 2002 orca series 4 fpgas m5 0 (tl) 10 io unused pl11a pl13a ? ? r5 7 (cl) 3 io unused pl16a pl20a ? ? t5 7 (cl) 3 io unused pl17a pl21a ? ? y2 7 (cl) 5 io unused pl23a pl27a ? ? aa2 7 (cl) 6 io unused pl24a pl28a ? ? aa3 7 (cl) 6 io unused pl25a pl29a ? ? ac 47 (cl) 8 io unused pl29a pl35a ? ? ad5 7 (cl) 8 io unused pl31a pl37a ? ? ae4 6 (bl) 1 io unused pl32a pl38a ? ? an7 6 (bl) 7 io unused pb7a pb9a ? ? al9 6 (bl) 7 io unused pb8a pb10a ? ? an8 6 (bl) 8 io unused pb9a pb11a ? ? an9 6 (bl) 8 io unused pb10a pb12a ? ? an14 6 (bl) 11 io unused pb15a pb19a ? ? al14 6 (bl) 11 io unused pb16a pb20a ? ? an15 5 (bc) 1 io unused pb17a pb21a ? ? al16 5 (bc) 1 io unused pb18a pb22a ? ? al20 5 (bc) 3 io unused pb22a pb27a ? ? ak19 5 (bc) 3 io unused pb23a pb28a ? ? ak20 5 (bc) 3 io unused pb24a pb29a ? ? ak21 5 (bc) 4 io unused pb25a pb30a ? ? an25 5 (bc) 6 io unused pb28a pb35a ? ? an26 5 (bc) 6 io unused pb29a pb36a ? ? am26 4 (br) 1 io unused pb30a pb37a ? ? d28 2 (tr) 6 io unused pt35d pt44d ? l16c_d1 b29 2 (tr) 6 io unused pt35c pt44c ? l16t_d1 e21 1 (tc) 3 io unused pt24a pt29a ? ? e20 1 (tc) 3 io unused pt23a pt28a ? ? d19 1 (tc) 3 io unused pt22a pt27a ? ? b13 1 (tc) 6 io unused pt14a pt19a ? ? d16 1 (tc) 5 io unused pt17a pt22a ? ? b15 1 (tc) 5 io unused pt16a pt21a ? ? b14 1 (tc) 6 io unused pt15a pt20a ? ? c10 0 (tl) 3 io unused pt10a pt12a ? ? e13 0 (tl) 3 io unused pt9a pt11a ? ? af30 4 (br) 7 io unused pr34a pr40a ? ? ah32 4 (br) 7 io unused pr33a pr39a ? ? ae30 4 (br) 7 io unused pr32a pr38a ? ? af32 4 (br) 8 io unused pr31a pr37a ? ? aa31 3 (cr) 2 io unused pr27c pr31a ? ? ad33 3 (cr) 2 io unused pr27d pr32b ? ? a c34 3 (cr) 2 io unused pr26c pr30a ? ? y31 3 (cr) 3 io unused pr24b pr29b ? ? aa34 3 (cr) 3 io unused pr24a pr28a ? ? ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
lattice semiconductor 139 data sheet november, 2002 orca series 4 fpgas y33 3 (cr) 4 io unused pr23a pr27a ? ? w32 3 (cr) 4 io unused pr22a pr26a ? ? u33 3 (cr) 5 io unused pr20a pr24a ? l12t_a0 u32 3 (cr) 5 io unused pr20b pr24b ? l12c_a0 t33 3 (cr) 5 io unused pr19a pr23a ? ? u30 3 (cr) 5 io unused pr18a pr22a ? ? r33 3 (cr) 5 io unused pr17a pr21a ? ? t30 3 (cr) 6 io unused pr16a pr20a ? ? r30 3 (cr) 6 io unused pr16b pr19b ? ? p30 3 (cr) 7 io unused pr15c pr17a ? ? n34 3 (cr) 7 io unused pr15d pr18b ? ? m30 2 (tr) 1 io unused pr9a pr11a ? ? l30 2 (tr) 1 io unused pr8a pr10a ? ? f34 2 (tr) 2 io unused pr7c pr9a ? ? d34 2 (tr) 3 io unused pr5c pr6a ? ? ap4 6 (bl) 5 io unused pb3a pb3a ? ? y3 7 (cl) ? v dd io7 v dd io7 v dd io7 v dd io7 ? ? ac 37 (cl) ? v dd io7 v dd io7 v dd io7 v dd io7 ? ? ad1 7 (cl) ? v dd io7 v dd io7 v dd io7 v dd io7 ? ? ap11 5 (bc) ? v dd io5 v dd io5 v dd io5 v dd io5 ? ? ap17 5 (bc) ? v dd io5 v dd io5 v dd io5 v dd io5 ? ? ap19 5 (bc) ? v dd io5 v dd io5 v dd io5 v dd io5 ? ? ap24 5 (bc) ? v dd io5 v dd io5 v dd io5 v dd io5 ? ? an32 4 (br) ? v dd io4 v dd io4 v dd io4 v dd io4 ? ? ap32 4 (br) ? v dd io4 v dd io4 v dd io4 v dd io4 ? ? y32 3 (cr) ? v dd io3 v dd io3 v dd io3 v dd io3 ? ? a c32 3 (cr) ? v dd io3 v dd io3 v dd io3 v dd io3 ? ? ad34 3 (cr) ? v dd io3 v dd io3 v dd io3 v dd io3 ? ? d32 2 (tr) ? v dd io2 v dd io2 v dd io2 v dd io2 ? ? e30 2 (tr) ? v dd io2 v dd io2 v dd io2 v dd io2 ? ? c12 1 (tc) ? v dd io1 v dd io1 v dd io1 v dd io1 ? ? c15 1 (tc) ? v dd io1 v dd io1 v dd io1 v dd io1 ? ? c20 1 (tc) ? v dd io1 v dd io1 v dd io1 v dd io1 ? ? c23 1 (tc) ? v dd io1 v dd io1 v dd io1 v dd io1 ? ? n16 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? y16 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? y17 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? w13 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? v13 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? u13 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? p18 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? p19 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? n17 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? n18 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
140 lattice semiconductor data sheet november, 2002 orca series 4 fpgas n19 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? p16 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? p17 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? r16 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? r17 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? r18 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? r19 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? t13 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? t14 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? t15 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? t20 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? t21 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? t22 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? u14 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? u15 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? u20 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? u21 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? u22 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? v14 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? v15 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? v20 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? v21 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? v22 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? w14 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? w15 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? w20 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? w21 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? w22 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? y18 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? y19 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? aa16 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? aa17 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? aa18 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? aa19 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? ab16 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? ab17 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? ab18 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? ab19 ? ? v dd 15 v dd 15 v dd 15 v dd 15 ? ? c3 ? ? vss vss vss vss ? ? c13 ? ? vss vss vss vss ? ? ap2 ? ? vss vss vss vss ? ? ap18 ? ? vss vss vss vss ? ? ap33 ? ? vss vss vss vss ? ? ap34 ? ? vss vss vss vss ? ? ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
lattice semiconductor 141 data sheet november, 2002 orca series 4 fpgas aa13 ? ? vss vss vss vss ? ? aa14 ? ? vss vss vss vss ? ? aa15 ? ? vss vss vss vss ? ? aa20 ? ? vss vss vss vss ? ? aa21 ? ? vss vss vss vss ? ? aa22 ? ? vss vss vss vss ? ? ab3 ? ? vss vss vss vss ? ? y14 ? ? vss vss vss vss ? ? u16 ? ? vss vss vss vss ? ? u17 ? ? vss vss vss vss ? ? u18 ? ? vss vss vss vss ? ? u19 ? ? vss vss vss vss ? ? v1 ? ? vss vss vss vss ? ? r14 ? ? vss vss vss vss ? ? r15 ? ? vss vss vss vss ? ? r20 ? ? vss vss vss vss ? ? n14 ? ? vss vss vss vss ? ? n15 ? ? vss vss vss vss ? ? n20 ? ? vss vss vss vss ? ? n21 ? ? vss vss vss vss ? ? n22 ? ? vss vss vss vss ? ? am33 4 (br) ? v dd io4 v dd io4 v dd io4 v dd io4 ? ? ta b le 69. 680-pin pbgam pinout bm680 v dd io bank vref group i/o or4e02 or4e04 or4e06 additional function p air
142 lattice semiconductor data sheet november, 2002 orca series 4 fpgas package ? thermal ? characteristics summary there ? are ? three ? thermal ? parameters ? that ? are ? in ? common ? use: ? ja , ? jc, ? and ? jc . ? it ? should ? be ? noted ? that ? all ? the ? parameters ? are ? affected, ? to ? varying ? degrees, ? by ? package ? design ? (including ? paddle ? size) ? and ? choice ? of ? materials, ? the ? amount ? of ? copper ? in ? the ? test ? board ? or ? system ? board, ? and ? system ? airflow. ja this ? is ? the ? thermal ? resistance ? from ? junction ? to ? ambient ? (theta-ja, ? r-theta, ? etc.): where ? t j ? is ? the ? junction ? temperature, ? t a, ? is ? the ? ambient ? air ? temperature, ? and ? q ? is ? the ? chip ? power. ? experimentally, ? ja ? is ? determined ? when ? a ? special ? thermal ? test ? die ? is ? assembled ? into ? the ? package ? of ? interest, ? and ? the ? part ? is ? mounted ? on ? the ? thermal ? test ? board. ? the ? diodes ? on ? the ? test ? chip ? are ? separately ? calibrated ? in ? an ? oven. ? the ? package/board ? is ? placed ? either ? in ? a ? jedec ? natural ? convection ? box ? or ? in ? the ? wind ? tunnel, ? the ? latter ? for ? forced ? con- vection ? measurements. ? a ? controlled ? amount ? of ? power ? (q) ? is ? dissipated ? in ? the ? test ? chip?s ? heater ? resistor, ? the ? chip?s ? temperature ? (t j ) ? is ? determined ? by ? the ? forward ? drop ? on ? the ? diodes, ? and ? the ? ambient ? temperature ? (t a ) ? is ? noted. ? note ? that ? ja ? is ? expressed ? in ? units ? of ? c/watt. jc this ? jedec ? designated ? parameter ? correlates ? the ? junction ? temperature ? to ? the ? case ? temperature. ? it ? is ? generally ? used ? to ? infer ? the ? junction ? temperature ? while ? the ? device ? is ? operating ? in ? the ? system. ? it ? is ? not ? considered ? a ? true ? ther- mal ? resistance, ? and ? it ? is ? defined ? by: where ? t c ? is ? the ? case ? temperature ? at ? top ? dead ? center, ? t j ? is ? the ? junction ? temperature, ? and ? q ? is ? the ? chip ? power. ? dur- ing ? the ? ja ? measurements ? described ? above, ? besides ? the ? other ? parameters ? measured, ? an ? additional ? temperature ? reading, ? t c , ? is ? made ? with ? a ? thermocouple ? attached ? at ? top-dead-center ? of ? the ? case. ? jc ? is ? also ? expressed ? in ? units ? of ? c/w. ? ja t j t a ? q ------------------- - = jc t j t c ? q -------------------- =
lattice semiconductor 143 data sheet november, 2002 orca series 4 fpgas jc this ? is ? the ? thermal ? resistance ? from ? junction ? to ? case. ? it ? is ? most ? often ? used ? when ? attaching ? a ? heat ? sink ? to ? the ? top ? of ? the ? package. ? it ? is ? defined ? by: the ? parameters ? in ? this ? equation ? have ? been ? defined ? above. ? however, ? the ? measurements ? are ? performed ? with ? the ? case ? of ? the ? part ? pressed ? against ? a ? water-cooled ? heat ? sink ? to ? draw ? most ? of ? the ? heat ? generated ? by ? the ? chip ? out ? the ? top ? of ? the ? package. ? it ? is ? this ? difference ? in ? the ? measurement ? process ? that ? differentiates ? jc ? from ? jc. ? jc ? is ? a ? true ? thermal ? resistance ? and ? is ? expressed ? in ? units ? of ? c/w. jb this ? is ? the ? thermal ? resistance ? from ? junction ? to ? board ? ( jl ). ? it ? is ? defined ? by: where ? t b ? is ? the ? temperature ? of ? the ? board ? adjacent ? to ? a ? lead ? measured ? with ? a ? thermocouple. ? the ? other ? parameters ? on ? the ? right-hand ? side ? have ? been ? defined ? above. ? this ? is ? considered ? a ? true ? thermal ? resistance, ? and ? the ? measure- ment ? is ? made ? with ? a ? water-cooled ? heat ? sink ? pressed ? against ? the ? board ? to ? draw ? most ? of ? the ? heat ? out ? of ? the ? leads. ? note ? that ? jb ? is ? expressed ? in ? units ? of ? c/w, ? and ? that ? this ? parameter ? and ? the ? way ? it ? is ? measured ? are ? still ? in ? jedec ? committee. jc t j t c ? q -------------------- = jb t j t b ? q ------------------- - =
144 lattice semiconductor data sheet november, 2002 orca series 4 fpgas package ? thermal ? characteristics t able ? 70. ? orca ? series ? 4 ? plastic ? package ? thermal ? guidelines note: the 416-pin pbgam and the 680-pin pbgam packages include 2 oz. copper plates package ? coplanarity the ? coplanarity ? limits ? of ? packages ? are ? as ? follows: pbga: 8.0 mils pbgam: 8.0 mils heat sink vendors for bga packages in some cases the power required by the customers application is greater than the package can dissipate. below, in alphabetical order, is a list of heat sink vendors who advertise heat sinks aimed at the bga market. ta b le 71. heat sink vendors package ja ? ( c/w) max ? power 0 ? fpm 200 ? fpm 500 ? fpm t ? = ? 70 ? c ? max t j ? = ? 125 ? c ? max 0 ? fpm ? (w) 352-pin ? pbga 19.0 16.0 15.0 2.9 416-pin ? pbgam 18.0 16.5 13.5 3.1 680-pin ? pbgam 13.4 11.5 10.5 4.1 v endor location phone aavid thermalloy concord, nh (603) 224-9988 chip coolers (tyco electronics) harrisburg, pa (800) 468-2023 ierc (cts corp.) burbank, ca (818) 842-7277 r-theta buffalo, ny (800) 388-5428 sanyo denki torrance, ca (310) 783-5400 wake eld thermal solutions pelham, nh (603) 635-2800
lattice semiconductor 145 data sheet november, 2002 orca series 4 fpgas pa ck ag e parasitics the ? electrical ? performance ? of ? an ? ic ? package, ? such ? as ? signal ? quality ? and ? noise ? sensitivity, ? is ? directly ? affected ? by ? the ? package ? parasitics. ? t able ? 72 ? lists ? eight ? parasitics ? associated ? with ? the ? orca ? packages. ? these ? parasitics ? represent ? the ? contributions ? of ? all ? components ? of ? a ? package, ? which ? include ? the ? bond ? wires, ? all ? internal ? package ? routing, ? and ? the ? external ? leads. four ? inductances ? in ? nh ? are ? listed: ? l sw ? and ? l sl, ? the ? self-inductance ? of ? the ? lead; ? and ? l mw ? and ? l ml , ? the ? mutual ? induc- tance ? to ? the ? nearest ? neighbor ? lead. ? these ? parameters ? are ? important ? in ? determining ? ground ? bounce ? noise ? and ? inductive ? crosstalk ? noise. ? three ? capacitances ? in ? pf ? are ? listed: ? c m , ? the ? mutual ? capacitance ? of ? the ? lead ? to ? the ? nearest ? neighbor ? lead; ? and ? c 1 ? and ? c 2 , ? the ? total ? capacitance ? of ? the ? lead ? to ? all ? other ? leads ? (all ? other ? leads ? are ? assumed ? to ? be ? grounded). ? these ? parameters ? are ? important ? in ? determining ? capacitive ? crosstalk ? and ? the ? capacitive ? loading ? effect ? of ? the ? lead. ? resistance ? values ? are ? in ? m ? . the ? parasitic ? values ? in ? t able ? 72 ? are ? for ? the ? circuit ? model ? of ? bond ? wire ? and ? package ? lead ? parasitics. ? if ? the ? mutual ? capacitance ? value ? is ? not ? used ? in ? the ? designer?s ? model, ? then ? the ? value ? listed ? as ? mutual ? capacitance ? should ? be ? added ? to ? each ? of ? the ? c 1 ? and ? c 2 ? capacitors. t able ? 72. ? orca ? series ? 4 ? package ? parasitics 5-3862(c)r2 figure ? 60. ? package ? parasitics package ? t ype l sw l mw r w c 1 c 2 c m l sl l ml 352-pin ? pbga 5.00 2.00 220 1.50 1.50 1.50 7?12 3?6 416-pin ? pbgam 3.52 0.80 235 0.40 1.00 0.25 1.5?5.0 0.5?1.3 680-pin ? pbgam 3.80 1.30 250 0.50 1.00 0.30 2.8?5 0.5?1.5 pad n l sw r w circuit board pad c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 l sl pad n + 1
146 lattice semiconductor data sheet november, 2002 orca series 4 fpgas package ? outline ? diagrams t erms ? and ? definitions basic ? size ? (bsc): ? the ? basic ? size ? of ? a ? dimension ? is ? the ? size ? from ? which ? the ? limits ? for ? that ? dimension ? are ? derived ? by ? the ? application ? of ? the ? allowance ? and ? the ? tolerance. design ? size: ? the ? design ? size ? of ? a ? dimension ? is ? the ? actual ? size ? of ? the ? design, ? including ? an ? allowance ? for ? fit ? and ? tol- erance. t ypical ? (typ): ? when ? specified ? after ? a ? dimension, ? this ? indicates ? the ? repeated ? design ? size ? if ? a ? tolerance ? is ? specified ? or ? repeated ? basic ? size ? if ? a ? tolerance ? is ? not ? specified. ? reference ? (ref): ? the ? reference ? dimension ? is ? an ? untoleranced ? dimension ? used ? for ? informational ? purposes ? only. ? it ? is ? a ? repeated ? dimension ? or ? one ? that ? can ? be ? derived ? from ? other ? values ? in ? the ? drawing. minimum ? (min) ? or ? maximum ? (max): ? indicates ? the ? minimum ? or ? maximum ? allowable ? size ? of ? a ? dimension. 2725(f)
lattice semiconductor 147 data sheet november, 2002 orca series 4 fpgas pa ck ag e outline diagrams 352-pin pbga dimensions are in millimeters. 5-4407(f) note: although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 fpga package. 0.56 0.06 1.17 0.05 2.33 0.21 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 35.00 +0.70 ?0.00 30.00 a1 ball identi fier zone af ae ad ac ab aa y w v u t r g 25 spaces @ 1.27 = 31.75 p n m l k j h 12 345678910 12 14 16 18 22 24 26 20 11 13 15 17 21 19 23 25 f e d c b a center array 25 spaces a1 ball 0.75 0.15 35.00 0.20 30.00 +0.70 ?0.00 0.20 @ 1.27 = 31.75 for thermal enhancement (optional) corner (see note below)
148 lattice semiconductor data sheet november, 2002 orca series 4 fpgas package ? outline ? diagrams ? (continued) 416-pin ? pbgam dimensions ? are ? in ? millimeters. 1 139(f) 5-4409(f) 0.61 ? ? 0.08 1.17 ? ? 0.05 2.28 ? ? 0.10 seating ? plane solder ? ball 0.50 ? ? 0.10 0.20 27.00 27.00 24.00 24.00 pin ? a1 ? corner af ae ad ac ab aa y w v u t r g 25 ? spaces ? @ ? 1.00 ? = ? 25.00 p n m l k j h 1 2 3 4 5 6 7 8 9 10 12 14 16 18 22 24 26 20 11 13 15 17 21 19 23 25 f e d c b a center ? array for ? thermal enhancement 25 ? spaces @ ? 1.00 ? = ? 25.00 a1 ? ball corner 0.63 ? ? 0.15
lattice semiconductor 149 data sheet november, 2002 orca series 4 fpgas pa ck ag e outline drawings (continued) 680-pin pbgam dimensions ? are ? in ? millimeters. 5-4406(f) seating plane solder ball 0.50 0.10 0.20 35.00 t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab a 19 30 26 28 24 32 22 20 18 468101 21416 2 34 52325 731 29 15 21 327 11 17 913 1 33 33 spaces @ 1.00 = 33.00 33 spaces a1 ball 0.64 0.15 a1 ball @ 1.00 = 33.00 corner 30.00 1.170 + 0.70 ? 0.00 35.00 30.00 + 0.70 ? 0.00 identifier zone 2.51 max 0.61 0.08
150 lattice semiconductor data sheet november, 2002 orca series 4 fpgas ordering information ta b le 73. device type options ta b le 74. recommended temperature range device voltage or4exx 1.5 v internal 3.3 v/2.5 v/1.8 v/1.5 v i/o symbol description ambient temperature junction temperature c commercial 0 ? c to +70 ? c0 ? c to +85 ? c i industrial ?40 ? c to +85 ? c ?40 ? c to +100 ? c device family or4e02 or4e04 or4e06 or4exx x x xx xxx speed grade package type ba = plastic ball grid array (pbga) bm = fine-pitch plastic ball grid array (pbgam) ball count grade c = commercial i = industrial
lattice semiconductor 151 data sheet november, 2002 orca series 4 fpgas ta b le 75. commercial ordering information device family part number speed grade package t ype ball count grade or4e02 or4e02-3ba352c 3 pbga 352 c or4e02-3bm416c 3 pbgam 416 c or4e02-3bm680c 3 pbgam 680 c or4e02-2ba352c 2 pbga 352 c or4e02-2bm416c 2 pbgam 416 c or4e02-2bm680c 2 pbgam 680 c or4e02-1ba352c 1 pbga 352 c or4e02-1bm416c 1 pbgam 416 c or4e02-1bm680c 1 pbgam 680 c or4e04 or4e04-3ba352c 3 pbga 352 c or4e04-3bm416c 3 pbgam 416 c or4e04-3bm680c 3 pbgam 680 c or4e04-2ba352c 2 pbga 352 c or4e04-2bm416c 2 pbgam 416 c or4e04-2bm680c 2 pbgam 680 c or4e04-1ba352c 1 pbga 352 c or4e04-1bm416c 1 pbgam 416 c or4e04-1bm680c 1 pbgam 680 c or4e06 or4e06-2ba352c 2 pbga 352 c or4e06-2bm680c 2 pbgam 680 c or4e06-1ba352c 1 pbga 352 c or4e06-1bm680c 1 pbgam 680 c
152 152 lattice semiconductor data sheet november, 2002 orca series 4 fpgas ta b le 76. industrial ordering information device family part number speed grade package t ype ball count grade or4e02 or4e02-2ba352i 2 pbga 352 i or4e02-2bm416i 2 pbgam 416 i OR4E02-2BM680I 2 pbgam 680 i or4e02-1ba352i 1 pbga 352 i or4e02-1bm416i 1 pbgam 416 i or4e02-1bm680i 1 pbgam 680 i or4e04 or4e04-2ba352i 2 pbga 352 i or4e04-2bm416i 2 pbgam 416 i or4e04-2bm680i 2 pbgam 680 i or4e04-1ba352i 1 pbga 352 i or4e04-1bm416i 1 pbgam 416 i or4e04-1bm680i 1 pbgam 680 i or4e06 or4e06-1ba352i 1 pbga 352 i or4e06-1bm680i 1 pbgam 680 i
lattice semiconductor 153 data sheet november, 2002 orca series 4 fpgas

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